diff --git a/SoC/evalsoc/Common/Source/IAR/startup_evalsoc.c b/SoC/evalsoc/Common/Source/IAR/startup_evalsoc.c
index f85bc215..91e07539 100644
--- a/SoC/evalsoc/Common/Source/IAR/startup_evalsoc.c
+++ b/SoC/evalsoc/Common/Source/IAR/startup_evalsoc.c
@@ -46,11 +46,13 @@ typedef void(*__fp)(void);
  * if you want to register vector interrupt with new entry,
  * you need to place it in writable section or create a ram vector
  * after bootup.
- * This alignment is set to 512 byte for up to 128 interrupts,
- * If you have more interrupts, you need to adjust the alignment
+ * TODO: This data_alignment is set to 512 byte for up to 128 interrupts,
+ * If you have more interrupts, you need to adjust the data_alignment
  * to other value, for details, please check mtvt csr documented
  * in Nuclei RISC-V ISA Spec
  */
+// TODO: change the data_alignment = 512 to match mtvt alignment requirement according to your eclic max interrupt number
+// TODO: place your interrupt handler into this vector table, important if your vector table is in flash
 #pragma data_alignment = 512
 static const __fp vector_base[SOC_INT_MAX] __attribute__((section (".mintvec"))) = {
     default_intexc_handler,
@@ -120,10 +122,13 @@ static const __fp vector_base[SOC_INT_MAX] __attribute__((section (".mintvec")))
 };
 
 #if defined(FLASH_RAM_VECTOR)
+// TODO: change the data_alignment = 512 to match mtvt alignment requirement according to your eclic max interrupt number
 #pragma data_alignment = 512
 static __fp vector_base_ram[SOC_INT_MAX] __attribute__((section (".mintvec_rw")));
 
 #if defined(__TEE_PRESENT) && (__TEE_PRESENT == 1)
+// TODO: change the data_alignment = 512 to match stvt alignment requirement according to your eclic max interrupt number
+#pragma data_alignment = 512
 static unsigned long vector_base_s_ram[SOC_INT_MAX] __attribute__((section (".sintvec_rw")));
 extern const unsigned long vector_table_s[SOC_INT_MAX];
 #endif
diff --git a/SoC/evalsoc/Common/Source/system_evalsoc.c b/SoC/evalsoc/Common/Source/system_evalsoc.c
index b9c33630..87456c03 100644
--- a/SoC/evalsoc/Common/Source/system_evalsoc.c
+++ b/SoC/evalsoc/Common/Source/system_evalsoc.c
@@ -91,7 +91,7 @@ void eclic_stip_handler(void) __attribute__((weak));
  * \brief vector interrupt storing ISRs for supervisor mode
  * \details
  *  vector_table_s is hold by stvt register, the address must align according
- *  to actual interrupt numbers as below, now align to 256 bytes considering we put 64 interrupts here
+ *  to actual interrupt numbers as below, now align to 512 bytes considering we put up to 128 interrupts here
  *  alignment must comply to table below if you increase or decrease vector interrupt number
  *  interrupt number      alignment
  *    0 to 16               64-byte
@@ -102,11 +102,13 @@ void eclic_stip_handler(void) __attribute__((weak));
  *    257 to 512              2KB
  *    513 to 1024             4KB
  */
+// TODO: change the aligned(512) to match stvt alignment requirement according to your eclic max interrupt number
 #ifndef __ICCRISCV__
-#define __SMODE_VECTOR_ATTR   __attribute__((section (".text.vtable_s"), aligned(256)))
+#define __SMODE_VECTOR_ATTR   __attribute__((section (".text.vtable_s"), aligned(512)))
 #else
-#define __SMODE_VECTOR_ATTR   __attribute__((section (".sintvec"), aligned(256)))
+#define __SMODE_VECTOR_ATTR   __attribute__((section (".sintvec"), aligned(512)))
 #endif
+// TODO: place your interrupt handler into this vector table, important if your vector table is in flash
 const unsigned long vector_table_s[SOC_INT_MAX] __SMODE_VECTOR_ATTR =
 {
     (unsigned long)(default_intexc_handler),        /* 0: Reserved */