From 8b09441916762b30b757f646cc66fca706494ca7 Mon Sep 17 00:00:00 2001
From: Lars Asplund <lars.anders.asplund@gmail.com>
Date: Thu, 28 Jan 2016 21:48:07 +0100
Subject: [PATCH] Replaced srl overloading with function call to work with
 Cadence Incisive.

---
 setup.py                       | 2 +-
 vunit/vhdl/check/src/check.vhd | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/setup.py b/setup.py
index 35950461a..09914a108 100644
--- a/setup.py
+++ b/setup.py
@@ -30,7 +30,7 @@ def find_all_files(directory, endings=None):
 
 setup(
     name='vunit_hdl',
-    version='0.51.2',
+    version='0.51.3',
     packages=['vunit',
               'vunit.com',
               'vunit.test',
diff --git a/vunit/vhdl/check/src/check.vhd b/vunit/vhdl/check/src/check.vhd
index 3cd135825..07123a8a0 100644
--- a/vunit/vhdl/check/src/check.vhd
+++ b/vunit/vhdl/check/src/check.vhd
@@ -18,7 +18,7 @@ use work.string_ops.all;
 
 package body check_pkg is
   type boolean_vector is array (natural range <>) of boolean;
-  function "srl" (
+  function logical_right_shift (
     constant arg   : boolean_vector;
     constant count : natural)
     return boolean_vector is
@@ -28,7 +28,7 @@ package body check_pkg is
     ret_val(count to ret_val'right) := temp(0 to ret_val'right - count);
 
     return ret_val;
-  end function "srl";
+  end function logical_right_shift;
   constant max_supported_num_of_bits_in_integer_implementation : natural := 256;
 
   function failed_expectation_msg (
@@ -1350,7 +1350,7 @@ package body check_pkg is
       else
         expected_events(0) := tracks(0);
       end if;
-      expected_events := expected_events srl 1;
+      expected_events := logical_right_shift(expected_events, 1);
     end procedure update_expectations_on_events_in_next_cycle;
 
     procedure verify_expected_events (