| counter | LUsmallv1w1 | LUsmallv1w128 | LUsmallv2w128 | LUsmallv4w1 | LUsmallv4w128 | LUsmallv4w256 |
|---|---|---|---|---|---|---|
| duration | 19980.0000 | 13783.0000 | 13757.0000 | 29232.0000 | 13813.0000 | 10837.0000 |
| task-clock | 20011.5100 | 13816.8300 | 13789.4300 | 29266.4000 | 13846.6800 | 10868.9400 |
| cycles | 69.9856 | 48.2901 | 48.1842 | 102.3110 | 48.4300 | 37.9677 |
| stalled-cycles-backend | 0.0120 | 0.0000 | 0.1697 | 0.0000 | 0.0058 | 0.0195 |
| stalled-cycles-frontend | 0.0279 | 0.0402 | 0.0449 | 0.0402 | 0.0355 | 0.0303 |
| iTLB-load-misses | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| iTLB-loads | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| instructions | 370.3973 | 190.7375 | 190.4040 | 279.6383 | 144.9638 | 80.5416 |
| branch-instructions | 46.4663 | 24.2109 | 24.2049 | 46.5354 | 24.2044 | 13.5101 |
| branch-misses | 0.2244 | 0.0784 | 0.0783 | 0.2300 | 0.0760 | 0.0179 |
| ex_ret_ops | 324.5968 | 167.2186 | 166.9407 | 233.8241 | 121.4499 | 68.1740 |
| ex_div_busy | 0.0026 | 0.0018 | 0.0018 | 0.0038 | 0.0018 | 0.0014 |
| ex_ret_mmx_fp_instr.sse_instr | 229.3173 | 116.1883 | 115.9525 | 138.3172 | 70.4379 | 36.8966 |
| fp_ret_sse_avx_ops.all | 90.9567 | 90.7030 | 90.7319 | 91.0648 | 90.7432 | 90.5699 |
| fp_num_mov_elim_scal_op.sse_mov_ops | 0.2758 | 0.3036 | 0.0039 | 0.0000 | 0.0000 | 0.0000 |
| fp_num_mov_elim_scal_op.sse_mov_ops_elim | 0.2757 | 0.3037 | 0.0039 | 0.0000 | 0.0000 | 0.0000 |
| fp_ret_sse_avx_ops.add_sub_flops | 45.3513 | 45.2554 | 45.2685 | 0.0000 | 0.0000 | 0.0000 |
| fp_ret_sse_avx_ops.mult_flops | 45.6504 | 45.5293 | 45.5503 | 0.2669 | 0.2658 | 0.2651 |
| fp_ret_sse_avx_ops.mac_flops | 0.0000 | 0.0000 | 0.0000 | 90.9095 | 90.5346 | 90.3647 |
| fp_ret_sse_avx_ops.div_flops | 0.0021 | 0.0021 | 0.0021 | 0.0021 | 0.0021 | 0.0021 |
| de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch | 236.5127 | 118.2171 | 118.1173 | 140.6576 | 71.6017 | 37.5083 |
| de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch | 97.7486 | 51.8566 | 51.9353 | 96.6701 | 51.6780 | 31.4432 |
| cache-misses | 1.7978 | 1.2778 | 1.2596 | 8.2729 | 1.4316 | 1.7682 |
| cache-references | 17.9562 | 16.7536 | 16.7505 | 21.5772 | 16.8910 | 16.2182 |
| all_data_cache_accesses | 142.4452 | 71.9788 | 72.0667 | 140.4463 | 71.7582 | 38.8296 |
| L1-dcache-load-misses | 8.0813 | 8.0671 | 8.0912 | 9.2643 | 8.0977 | 8.0422 |
| L1-dcache-loads | 138.6292 | 79.8499 | 79.8860 | 138.7596 | 79.8736 | 51.6972 |
| L1-dcache-prefetches | 1.0717 | 0.9916 | 1.0197 | 7.1180 | 0.8981 | 0.8676 |
| L1-icache-load-misses | 0.0002 | 0.0004 | 0.0009 | 0.0003 | 0.0001 | 0.0007 |
| L1-icache-loads | 0.0257 | 0.0791 | 0.1197 | 0.0357 | 0.0197 | 0.0792 |
| l2_cache_accesses_from_dc_misses | 8.0842 | 8.0706 | 8.0922 | 9.2717 | 8.1020 | 8.0441 |
| l2_cache_hits_from_dc_misses | 7.6136 | 7.4308 | 7.4911 | 8.9503 | 7.4754 | 7.1149 |
| l2_cache_misses_from_dc_misses | 0.3364 | 0.4515 | 0.4214 | 0.1760 | 0.4150 | 0.6719 |
| dTLB-load-misses | 0.0000 | 0.0007 | 0.0009 | 0.0015 | 0.0000 | 0.0000 |
| dTLB-loads | 0.5650 | 0.5745 | 0.5746 | 0.5700 | 0.5729 | 0.5719 |
| ls_dispatch.ld_dispatch | 95.3725 | 48.5742 | 48.6065 | 93.9515 | 48.4032 | 26.6993 |
| ls_dispatch.ld_st_dispatch | 0.0023 | 0.0066 | 0.0064 | 0.0033 | 0.0068 | 0.0039 |
| ls_dispatch.store_dispatch | 47.0762 | 23.4312 | 23.4649 | 46.4917 | 23.3650 | 12.1286 |