From c4429566b6496fc98994a7b88d64c0dd626e6985 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 1 May 2024 11:11:45 +0100 Subject: [PATCH 1/5] JIT ARM64-SVE: Add simple bitwise ops And,AndAcross,Or,OrAcross,Xor,XorAcross --- src/coreclr/jit/codegenarm64test.cpp | 38 +- src/coreclr/jit/emitarm64sve.cpp | 11 +- src/coreclr/jit/hwintrinsiclistarm64sve.h | 6 + .../Arm/Sve.PlatformNotSupported.cs | 548 ++++++++++++++++++ .../src/System/Runtime/Intrinsics/Arm/Sve.cs | 548 ++++++++++++++++++ .../ref/System.Runtime.Intrinsics.cs | 55 ++ .../GenerateHWIntrinsicTests_Arm.cs | 54 ++ .../HardwareIntrinsics/Arm/Shared/Helpers.cs | 48 ++ 8 files changed, 1285 insertions(+), 23 deletions(-) diff --git a/src/coreclr/jit/codegenarm64test.cpp b/src/coreclr/jit/codegenarm64test.cpp index 2057a72323bf7..7fda65ddc6aee 100644 --- a/src/coreclr/jit/codegenarm64test.cpp +++ b/src/coreclr/jit/codegenarm64test.cpp @@ -4802,11 +4802,11 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_D); // CLASTB ., , ., . // IF_SVE_CN_3A - theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_2BYTE, REG_V12, REG_P1, REG_V15, INS_OPTS_SCALABLE_H, + theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_SCALABLE, REG_V12, REG_P1, REG_V15, INS_OPTS_SCALABLE_H, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // CLASTA , , , . - theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_V13, REG_P2, REG_V16, INS_OPTS_SCALABLE_S, + theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_SCALABLE, REG_V13, REG_P2, REG_V16, INS_OPTS_SCALABLE_S, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // CLASTB , , , . - theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_V14, REG_P0, REG_V17, INS_OPTS_SCALABLE_D, + theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_SCALABLE, REG_V14, REG_P0, REG_V17, INS_OPTS_SCALABLE_D, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // CLASTB , , , . // IF_SVE_CO_3A @@ -5292,13 +5292,13 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_H); // FNMLS ., /M, ., . // IF_SVE_AF_3A - theEmitter->emitIns_R_R_R(INS_sve_andv, EA_1BYTE, REG_V0, REG_P0, REG_V0, + theEmitter->emitIns_R_R_R(INS_sve_andv, EA_SCALABLE, REG_V0, REG_P0, REG_V0, INS_OPTS_SCALABLE_B); // ANDV , , . - theEmitter->emitIns_R_R_R(INS_sve_eorv, EA_2BYTE, REG_V1, REG_P1, REG_V1, + theEmitter->emitIns_R_R_R(INS_sve_eorv, EA_SCALABLE, REG_V1, REG_P1, REG_V1, INS_OPTS_SCALABLE_H); // EORV , , . - theEmitter->emitIns_R_R_R(INS_sve_orv, EA_4BYTE, REG_V2, REG_P2, REG_V2, + theEmitter->emitIns_R_R_R(INS_sve_orv, EA_SCALABLE, REG_V2, REG_P2, REG_V2, INS_OPTS_SCALABLE_S); // ORV , , . - theEmitter->emitIns_R_R_R(INS_sve_orv, EA_8BYTE, REG_V3, REG_P3, REG_V3, + theEmitter->emitIns_R_R_R(INS_sve_orv, EA_SCALABLE, REG_V3, REG_P3, REG_V3, INS_OPTS_SCALABLE_D); // ORV , , . // IF_SVE_AG_3A @@ -5328,13 +5328,13 @@ void CodeGen::genArm64EmitterUnitTestsSve() #endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED // IF_SVE_AK_3A - theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_8BYTE, REG_V15, REG_P7, REG_V4, + theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_SCALABLE, REG_V15, REG_P7, REG_V4, INS_OPTS_SCALABLE_D); // SMAXV , , . - theEmitter->emitIns_R_R_R(INS_sve_sminv, EA_4BYTE, REG_V16, REG_P6, REG_V14, + theEmitter->emitIns_R_R_R(INS_sve_sminv, EA_SCALABLE, REG_V16, REG_P6, REG_V14, INS_OPTS_SCALABLE_S); // SMINV , , . - theEmitter->emitIns_R_R_R(INS_sve_umaxv, EA_2BYTE, REG_V17, REG_P5, REG_V24, + theEmitter->emitIns_R_R_R(INS_sve_umaxv, EA_SCALABLE, REG_V17, REG_P5, REG_V24, INS_OPTS_SCALABLE_H); // UMAXV , , . - theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_1BYTE, REG_V18, REG_P4, REG_V31, + theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_SCALABLE, REG_V18, REG_P4, REG_V31, INS_OPTS_SCALABLE_B); // UMINV , , . // IF_SVE_AL_3A @@ -6222,13 +6222,13 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_D); // COMPACT ., , . // IF_SVE_CP_3A - theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_1BYTE, REG_V14, REG_P1, REG_V11, INS_OPTS_SCALABLE_B, + theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_SCALABLE, REG_V14, REG_P1, REG_V11, INS_OPTS_SCALABLE_B, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // CPY ., /M, - theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V13, REG_P2, REG_V10, INS_OPTS_SCALABLE_S, + theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_SCALABLE, REG_V13, REG_P2, REG_V10, INS_OPTS_SCALABLE_S, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // CPY ., /M, - theEmitter->emitIns_R_R_R(INS_sve_mov, EA_2BYTE, REG_V12, REG_P3, REG_V9, INS_OPTS_SCALABLE_H, + theEmitter->emitIns_R_R_R(INS_sve_mov, EA_SCALABLE, REG_V12, REG_P3, REG_V9, INS_OPTS_SCALABLE_H, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // MOV ., /M, - theEmitter->emitIns_R_R_R(INS_sve_mov, EA_8BYTE, REG_V11, REG_P4, REG_V8, INS_OPTS_SCALABLE_D, + theEmitter->emitIns_R_R_R(INS_sve_mov, EA_SCALABLE, REG_V11, REG_P4, REG_V8, INS_OPTS_SCALABLE_D, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // MOV ., /M, // IF_SVE_CQ_3A @@ -6243,13 +6243,13 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_B); // MOV ., /M, // IF_SVE_CR_3A - theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_1BYTE, REG_V6, REG_P1, REG_V27, INS_OPTS_SCALABLE_B, + theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_SCALABLE, REG_V6, REG_P1, REG_V27, INS_OPTS_SCALABLE_B, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // LASTA , , . - theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_2BYTE, REG_V5, REG_P2, REG_V26, INS_OPTS_SCALABLE_H, + theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_SCALABLE, REG_V5, REG_P2, REG_V26, INS_OPTS_SCALABLE_H, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // LASTA , , . - theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_V4, REG_P3, REG_V25, INS_OPTS_SCALABLE_S, + theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_SCALABLE, REG_V4, REG_P3, REG_V25, INS_OPTS_SCALABLE_S, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // LASTB , , . - theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_V3, REG_P4, REG_V24, INS_OPTS_SCALABLE_D, + theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_SCALABLE, REG_V3, REG_P4, REG_V24, INS_OPTS_SCALABLE_D, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // LASTB , , . // IF_SVE_CS_3A diff --git a/src/coreclr/jit/emitarm64sve.cpp b/src/coreclr/jit/emitarm64sve.cpp index f7aa628e3f835..2ac4d73b2c018 100644 --- a/src/coreclr/jit/emitarm64sve.cpp +++ b/src/coreclr/jit/emitarm64sve.cpp @@ -2919,7 +2919,10 @@ void emitter::emitInsSve_R_R_R(instruction ins, if (sopt == INS_SCALABLE_OPTS_UNPREDICATED) { - assert(opt == INS_OPTS_SCALABLE_D); + // The instruction only has a .D variant. However, this doesn't matter as + // it operates on bits not lanes. Effectively this means all standard opt + // sizes are supported. + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg2)); // nnnnn fmt = IF_SVE_AU_3A; } @@ -3728,7 +3731,7 @@ void emitter::emitInsSve_R_R_R(instruction ins, else if (sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) { assert(isFloatReg(reg1)); - assert(isValidVectorElemsize(size)); + assert(isScalableVectorSize(size)); fmt = IF_SVE_CN_3A; } else @@ -3748,7 +3751,7 @@ void emitter::emitInsSve_R_R_R(instruction ins, if (sopt == INS_SCALABLE_OPTS_UNPREDICATED) { assert(ins == INS_sve_mov); - assert(opt == INS_OPTS_SCALABLE_D); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); // ddddd assert(isVectorRegister(reg2)); // nnnnn assert(isVectorRegister(reg3)); // mmmmm @@ -12622,7 +12625,7 @@ void emitter::emitInsSveSanityCheck(instrDesc* id) assert(isVectorRegister(id->idReg1())); // ddddd assert(isLowPredicateRegister(id->idReg2())); // ggg assert(isVectorRegister(id->idReg3())); // mmmmm - assert(isValidVectorElemsize(id->idOpSize())); + assert(isScalableVectorSize(id->idOpSize())); break; // Scalable to FP SIMD scalar. diff --git a/src/coreclr/jit/hwintrinsiclistarm64sve.h b/src/coreclr/jit/hwintrinsiclistarm64sve.h index 6a8346c216282..7bb1789175a1a 100644 --- a/src/coreclr/jit/hwintrinsiclistarm64sve.h +++ b/src/coreclr/jit/hwintrinsiclistarm64sve.h @@ -20,6 +20,8 @@ HARDWARE_INTRINSIC(Sve, Abs, -1, -1, false, {INS_sve_abs, INS_invalid, INS_sve_abs, INS_invalid, INS_sve_abs, INS_invalid, INS_sve_abs, INS_invalid, INS_sve_fabs, INS_sve_fabs}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation) HARDWARE_INTRINSIC(Sve, Add, -1, -1, false, {INS_sve_add, INS_sve_add, INS_sve_add, INS_sve_add, INS_sve_add, INS_sve_add, INS_sve_add, INS_sve_add, INS_sve_fadd, INS_sve_fadd}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, AddAcross, -1, 1, true, {INS_sve_saddv, INS_sve_uaddv, INS_sve_saddv, INS_sve_uaddv, INS_sve_saddv, INS_sve_uaddv, INS_sve_uaddv, INS_sve_uaddv, INS_sve_faddv, INS_sve_faddv}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation) +HARDWARE_INTRINSIC(Sve, And, -1, -1, false, {INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation) +HARDWARE_INTRINSIC(Sve, AndAcross, -1, -1, false, {INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, ConditionalSelect, -1, 3, true, {INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_SupportsContainment) HARDWARE_INTRINSIC(Sve, Count16BitElements, 0, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_cnth, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_Scalable|HW_Flag_HasEnumOperand|HW_Flag_SpecialCodeGen|HW_Flag_NoFloatingPointUsed) HARDWARE_INTRINSIC(Sve, Count32BitElements, 0, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_cntw, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_Scalable|HW_Flag_HasEnumOperand|HW_Flag_SpecialCodeGen|HW_Flag_NoFloatingPointUsed) @@ -70,6 +72,8 @@ HARDWARE_INTRINSIC(Sve, LoadVectorUInt16ZeroExtendToUInt64, HARDWARE_INTRINSIC(Sve, LoadVectorUInt32ZeroExtendToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_ld1w, INS_invalid, INS_invalid, INS_invalid}, HW_Category_MemoryLoad, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, LoadVectorUInt32ZeroExtendToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_ld1w, INS_invalid, INS_invalid}, HW_Category_MemoryLoad, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, Multiply, -1, 2, true, {INS_sve_mul, INS_sve_mul, INS_sve_mul, INS_sve_mul, INS_sve_mul, INS_sve_mul, INS_sve_mul, INS_sve_mul, INS_sve_fmul, INS_sve_fmul}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics) +HARDWARE_INTRINSIC(Sve, Or, -1, -1, false, {INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation) +HARDWARE_INTRINSIC(Sve, OrAcross, -1, -1, false, {INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, SignExtend16, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sxth, INS_invalid, INS_sve_sxth, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, SignExtend32, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sxtw, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, SignExtend8, -1, -1, false, {INS_invalid, INS_invalid, INS_sve_sxtb, INS_invalid, INS_sve_sxtb, INS_invalid, INS_sve_sxtb, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) @@ -78,6 +82,8 @@ HARDWARE_INTRINSIC(Sve, SignExtendWideningUpper, HARDWARE_INTRINSIC(Sve, Subtract, -1, 2, true, {INS_sve_sub, INS_sve_sub, INS_sve_sub, INS_sve_sub, INS_sve_sub, INS_sve_sub, INS_sve_sub, INS_sve_sub, INS_sve_fsub, INS_sve_fsub}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(Sve, UnzipEven, -1, 2, true, {INS_sve_uzp1, INS_sve_uzp1, INS_sve_uzp1, INS_sve_uzp1, INS_sve_uzp1, INS_sve_uzp1, INS_sve_uzp1, INS_sve_uzp1, INS_sve_uzp1, INS_sve_uzp1}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen) HARDWARE_INTRINSIC(Sve, UnzipOdd, -1, 2, true, {INS_sve_uzp2, INS_sve_uzp2, INS_sve_uzp2, INS_sve_uzp2, INS_sve_uzp2, INS_sve_uzp2, INS_sve_uzp2, INS_sve_uzp2, INS_sve_uzp2, INS_sve_uzp2}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen) +HARDWARE_INTRINSIC(Sve, Xor, -1, -1, false, {INS_sve_eor, INS_sve_eor, INS_sve_eor, INS_sve_eor, INS_sve_eor, INS_sve_eor, INS_sve_eor, INS_sve_eor, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation) +HARDWARE_INTRINSIC(Sve, XorAcross, -1, -1, false, {INS_sve_eorv, INS_sve_eorv, INS_sve_eorv, INS_sve_eorv, INS_sve_eorv, INS_sve_eorv, INS_sve_eorv, INS_sve_eorv, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, ZeroExtend16, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_uxth, INS_invalid, INS_sve_uxth, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, ZeroExtend32, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_uxtw, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, ZeroExtend8, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_sve_uxtb, INS_invalid, INS_sve_uxtb, INS_invalid, INS_sve_uxtb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs index 5cc1d3df2f7cb..14c4274a7aaf4 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs @@ -211,6 +211,188 @@ internal Arm64() { } public static unsafe Vector AddAcross(Vector value) { throw new PlatformNotSupportedException(); } + /// And : Bitwise AND + + /// + /// svuint8_t svand[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// MOVPRFX Zresult, Zop1; AND Zresult.B, Pg/M, Zresult.B, Zop2.B + /// svuint8_t svand[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// AND Ztied2.B, Pg/M, Ztied2.B, Zop1.B + /// AND Zresult.D, Zop1.D, Zop2.D + /// svuint8_t svand[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; AND Zresult.B, Pg/M, Zresult.B, Zop2.B + /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; AND Zresult.B, Pg/M, Zresult.B, Zop1.B + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint16_t svand[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2) + /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// MOVPRFX Zresult, Zop1; AND Zresult.H, Pg/M, Zresult.H, Zop2.H + /// svint16_t svand[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2) + /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// AND Ztied2.H, Pg/M, Ztied2.H, Zop1.H + /// AND Zresult.D, Zop1.D, Zop2.D + /// svint16_t svand[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) + /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; AND Zresult.H, Pg/M, Zresult.H, Zop2.H + /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; AND Zresult.H, Pg/M, Zresult.H, Zop1.H + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint32_t svand[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2) + /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// MOVPRFX Zresult, Zop1; AND Zresult.S, Pg/M, Zresult.S, Zop2.S + /// svint32_t svand[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2) + /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// AND Ztied2.S, Pg/M, Ztied2.S, Zop1.S + /// AND Zresult.D, Zop1.D, Zop2.D + /// svint32_t svand[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) + /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; AND Zresult.S, Pg/M, Zresult.S, Zop2.S + /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; AND Zresult.S, Pg/M, Zresult.S, Zop1.S + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint64_t svand[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2) + /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// MOVPRFX Zresult, Zop1; AND Zresult.D, Pg/M, Zresult.D, Zop2.D + /// svint64_t svand[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2) + /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// AND Ztied2.D, Pg/M, Ztied2.D, Zop1.D + /// AND Zresult.D, Zop1.D, Zop2.D + /// svint64_t svand[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) + /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; AND Zresult.D, Pg/M, Zresult.D, Zop2.D + /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; AND Zresult.D, Pg/M, Zresult.D, Zop1.D + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint8_t svand[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2) + /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// MOVPRFX Zresult, Zop1; AND Zresult.B, Pg/M, Zresult.B, Zop2.B + /// svint8_t svand[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2) + /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// AND Ztied2.B, Pg/M, Ztied2.B, Zop1.B + /// AND Zresult.D, Zop1.D, Zop2.D + /// svint8_t svand[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) + /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; AND Zresult.B, Pg/M, Zresult.B, Zop2.B + /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; AND Zresult.B, Pg/M, Zresult.B, Zop1.B + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svuint16_t svand[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// MOVPRFX Zresult, Zop1; AND Zresult.H, Pg/M, Zresult.H, Zop2.H + /// svuint16_t svand[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// AND Ztied2.H, Pg/M, Ztied2.H, Zop1.H + /// AND Zresult.D, Zop1.D, Zop2.D + /// svuint16_t svand[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; AND Zresult.H, Pg/M, Zresult.H, Zop2.H + /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; AND Zresult.H, Pg/M, Zresult.H, Zop1.H + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svuint32_t svand[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// MOVPRFX Zresult, Zop1; AND Zresult.S, Pg/M, Zresult.S, Zop2.S + /// svuint32_t svand[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// AND Ztied2.S, Pg/M, Ztied2.S, Zop1.S + /// AND Zresult.D, Zop1.D, Zop2.D + /// svuint32_t svand[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; AND Zresult.S, Pg/M, Zresult.S, Zop2.S + /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; AND Zresult.S, Pg/M, Zresult.S, Zop1.S + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svuint64_t svand[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// MOVPRFX Zresult, Zop1; AND Zresult.D, Pg/M, Zresult.D, Zop2.D + /// svuint64_t svand[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// AND Ztied2.D, Pg/M, Ztied2.D, Zop1.D + /// AND Zresult.D, Zop1.D, Zop2.D + /// svuint64_t svand[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; AND Zresult.D, Pg/M, Zresult.D, Zop2.D + /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; AND Zresult.D, Pg/M, Zresult.D, Zop1.D + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + + /// AndAcross : Bitwise AND reduction to scalar + + /// + /// uint8_t svandv[_u8](svbool_t pg, svuint8_t op) + /// ANDV Bresult, Pg, Zop.B + /// + public static unsafe Vector AndAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// int16_t svandv[_s16](svbool_t pg, svint16_t op) + /// ANDV Hresult, Pg, Zop.H + /// + public static unsafe Vector AndAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// int32_t svandv[_s32](svbool_t pg, svint32_t op) + /// ANDV Sresult, Pg, Zop.S + /// + public static unsafe Vector AndAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// int64_t svandv[_s64](svbool_t pg, svint64_t op) + /// ANDV Dresult, Pg, Zop.D + /// + public static unsafe Vector AndAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// int8_t svandv[_s8](svbool_t pg, svint8_t op) + /// ANDV Bresult, Pg, Zop.B + /// + public static unsafe Vector AndAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// uint16_t svandv[_u16](svbool_t pg, svuint16_t op) + /// ANDV Hresult, Pg, Zop.H + /// + public static unsafe Vector AndAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// uint32_t svandv[_u32](svbool_t pg, svuint32_t op) + /// ANDV Sresult, Pg, Zop.S + /// + public static unsafe Vector AndAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// uint64_t svandv[_u64](svbool_t pg, svuint64_t op) + /// ANDV Dresult, Pg, Zop.D + /// + public static unsafe Vector AndAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// ConditionalSelect : Conditionally select elements /// @@ -1072,6 +1254,189 @@ internal Arm64() { } /// public static unsafe Vector Multiply(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// Or : Bitwise inclusive OR + + /// + /// svuint8_t svorr[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// MOVPRFX Zresult, Zop1; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// svuint8_t svorr[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// ORR Ztied2.B, Pg/M, Ztied2.B, Zop1.B + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svuint8_t svorr[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; ORR Zresult.B, Pg/M, Zresult.B, Zop1.B + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint16_t svorr[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2) + /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// MOVPRFX Zresult, Zop1; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// svint16_t svorr[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2) + /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// ORR Ztied2.H, Pg/M, Ztied2.H, Zop1.H + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svint16_t svorr[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) + /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; ORR Zresult.H, Pg/M, Zresult.H, Zop1.H + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint32_t svorr[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2) + /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// MOVPRFX Zresult, Zop1; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// svint32_t svorr[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2) + /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// ORR Ztied2.S, Pg/M, Ztied2.S, Zop1.S + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svint32_t svorr[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) + /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; ORR Zresult.S, Pg/M, Zresult.S, Zop1.S + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint64_t svorr[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2) + /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// MOVPRFX Zresult, Zop1; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// svint64_t svorr[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2) + /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// ORR Ztied2.D, Pg/M, Ztied2.D, Zop1.D + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svint64_t svorr[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) + /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; ORR Zresult.D, Pg/M, Zresult.D, Zop1.D + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint8_t svorr[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2) + /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// MOVPRFX Zresult, Zop1; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// svint8_t svorr[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2) + /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// ORR Ztied2.B, Pg/M, Ztied2.B, Zop1.B + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svint8_t svorr[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) + /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; ORR Zresult.B, Pg/M, Zresult.B, Zop1.B + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svuint16_t svorr[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// MOVPRFX Zresult, Zop1; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// svuint16_t svorr[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// ORR Ztied2.H, Pg/M, Ztied2.H, Zop1.H + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svuint16_t svorr[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; ORR Zresult.H, Pg/M, Zresult.H, Zop1.H + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svuint32_t svorr[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// MOVPRFX Zresult, Zop1; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// svuint32_t svorr[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// ORR Ztied2.S, Pg/M, Ztied2.S, Zop1.S + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svuint32_t svorr[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; ORR Zresult.S, Pg/M, Zresult.S, Zop1.S + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svuint64_t svorr[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// MOVPRFX Zresult, Zop1; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// svuint64_t svorr[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// ORR Ztied2.D, Pg/M, Ztied2.D, Zop1.D + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svuint64_t svorr[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; ORR Zresult.D, Pg/M, Zresult.D, Zop1.D + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + + /// OrAcross : Bitwise inclusive OR reduction to scalar + + /// + /// uint8_t svorv[_u8](svbool_t pg, svuint8_t op) + /// ORV Bresult, Pg, Zop.B + /// + public static unsafe Vector OrAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// int16_t svorv[_s16](svbool_t pg, svint16_t op) + /// ORV Hresult, Pg, Zop.H + /// + public static unsafe Vector OrAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// int32_t svorv[_s32](svbool_t pg, svint32_t op) + /// ORV Sresult, Pg, Zop.S + /// + public static unsafe Vector OrAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// int64_t svorv[_s64](svbool_t pg, svint64_t op) + /// ORV Dresult, Pg, Zop.D + /// + public static unsafe Vector OrAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// int8_t svorv[_s8](svbool_t pg, svint8_t op) + /// ORV Bresult, Pg, Zop.B + /// + public static unsafe Vector OrAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// uint16_t svorv[_u16](svbool_t pg, svuint16_t op) + /// ORV Hresult, Pg, Zop.H + /// + public static unsafe Vector OrAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// uint32_t svorv[_u32](svbool_t pg, svuint32_t op) + /// ORV Sresult, Pg, Zop.S + /// + public static unsafe Vector OrAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// uint64_t svorv[_u64](svbool_t pg, svuint64_t op) + /// ORV Dresult, Pg, Zop.D + /// + public static unsafe Vector OrAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// SignExtend16 : Sign-extend the low 16 bits /// @@ -1432,6 +1797,189 @@ internal Arm64() { } /// public static unsafe Vector UnzipOdd(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// Xor : Bitwise exclusive OR + + /// + /// svuint8_t sveor[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// MOVPRFX Zresult, Zop1; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// svuint8_t sveor[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// EOR Ztied2.B, Pg/M, Ztied2.B, Zop1.B + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svuint8_t sveor[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; EOR Zresult.B, Pg/M, Zresult.B, Zop1.B + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint16_t sveor[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2) + /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// MOVPRFX Zresult, Zop1; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// svint16_t sveor[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2) + /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// EOR Ztied2.H, Pg/M, Ztied2.H, Zop1.H + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svint16_t sveor[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) + /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; EOR Zresult.H, Pg/M, Zresult.H, Zop1.H + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint32_t sveor[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2) + /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// MOVPRFX Zresult, Zop1; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// svint32_t sveor[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2) + /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// EOR Ztied2.S, Pg/M, Ztied2.S, Zop1.S + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svint32_t sveor[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) + /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; EOR Zresult.S, Pg/M, Zresult.S, Zop1.S + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint64_t sveor[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2) + /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// MOVPRFX Zresult, Zop1; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// svint64_t sveor[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2) + /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// EOR Ztied2.D, Pg/M, Ztied2.D, Zop1.D + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svint64_t sveor[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) + /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; EOR Zresult.D, Pg/M, Zresult.D, Zop1.D + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint8_t sveor[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2) + /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// MOVPRFX Zresult, Zop1; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// svint8_t sveor[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2) + /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// EOR Ztied2.B, Pg/M, Ztied2.B, Zop1.B + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svint8_t sveor[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) + /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; EOR Zresult.B, Pg/M, Zresult.B, Zop1.B + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svuint16_t sveor[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// MOVPRFX Zresult, Zop1; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// svuint16_t sveor[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// EOR Ztied2.H, Pg/M, Ztied2.H, Zop1.H + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svuint16_t sveor[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; EOR Zresult.H, Pg/M, Zresult.H, Zop1.H + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svuint32_t sveor[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// MOVPRFX Zresult, Zop1; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// svuint32_t sveor[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// EOR Ztied2.S, Pg/M, Ztied2.S, Zop1.S + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svuint32_t sveor[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; EOR Zresult.S, Pg/M, Zresult.S, Zop1.S + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svuint64_t sveor[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// MOVPRFX Zresult, Zop1; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// svuint64_t sveor[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// EOR Ztied2.D, Pg/M, Ztied2.D, Zop1.D + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svuint64_t sveor[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; EOR Zresult.D, Pg/M, Zresult.D, Zop1.D + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + + /// XorAcross : Bitwise exclusive OR reduction to scalar + + /// + /// uint8_t sveorv[_u8](svbool_t pg, svuint8_t op) + /// EORV Bresult, Pg, Zop.B + /// + public static unsafe Vector XorAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// int16_t sveorv[_s16](svbool_t pg, svint16_t op) + /// EORV Hresult, Pg, Zop.H + /// + public static unsafe Vector XorAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// int32_t sveorv[_s32](svbool_t pg, svint32_t op) + /// EORV Sresult, Pg, Zop.S + /// + public static unsafe Vector XorAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// int64_t sveorv[_s64](svbool_t pg, svint64_t op) + /// EORV Dresult, Pg, Zop.D + /// + public static unsafe Vector XorAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// int8_t sveorv[_s8](svbool_t pg, svint8_t op) + /// EORV Bresult, Pg, Zop.B + /// + public static unsafe Vector XorAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// uint16_t sveorv[_u16](svbool_t pg, svuint16_t op) + /// EORV Hresult, Pg, Zop.H + /// + public static unsafe Vector XorAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// uint32_t sveorv[_u32](svbool_t pg, svuint32_t op) + /// EORV Sresult, Pg, Zop.S + /// + public static unsafe Vector XorAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// + /// uint64_t sveorv[_u64](svbool_t pg, svuint64_t op) + /// EORV Dresult, Pg, Zop.D + /// + public static unsafe Vector XorAcross(Vector value) { throw new PlatformNotSupportedException(); } + + /// ZeroExtend16 : Zero-extend the low 16 bits /// diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs index d195dd03dfb48..29c0a836f5401 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs @@ -240,6 +240,188 @@ internal Arm64() { } public static unsafe Vector AddAcross(Vector value) => AddAcross(value); + /// And : Bitwise AND + + /// + /// svuint8_t svand[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// MOVPRFX Zresult, Zop1; AND Zresult.B, Pg/M, Zresult.B, Zop2.B + /// svuint8_t svand[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// AND Ztied2.B, Pg/M, Ztied2.B, Zop1.B + /// AND Zresult.D, Zop1.D, Zop2.D + /// svuint8_t svand[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; AND Zresult.B, Pg/M, Zresult.B, Zop2.B + /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; AND Zresult.B, Pg/M, Zresult.B, Zop1.B + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) => And(left, right); + + /// + /// svint16_t svand[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2) + /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// MOVPRFX Zresult, Zop1; AND Zresult.H, Pg/M, Zresult.H, Zop2.H + /// svint16_t svand[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2) + /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// AND Ztied2.H, Pg/M, Ztied2.H, Zop1.H + /// AND Zresult.D, Zop1.D, Zop2.D + /// svint16_t svand[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) + /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; AND Zresult.H, Pg/M, Zresult.H, Zop2.H + /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; AND Zresult.H, Pg/M, Zresult.H, Zop1.H + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) => And(left, right); + + /// + /// svint32_t svand[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2) + /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// MOVPRFX Zresult, Zop1; AND Zresult.S, Pg/M, Zresult.S, Zop2.S + /// svint32_t svand[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2) + /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// AND Ztied2.S, Pg/M, Ztied2.S, Zop1.S + /// AND Zresult.D, Zop1.D, Zop2.D + /// svint32_t svand[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) + /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; AND Zresult.S, Pg/M, Zresult.S, Zop2.S + /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; AND Zresult.S, Pg/M, Zresult.S, Zop1.S + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) => And(left, right); + + /// + /// svint64_t svand[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2) + /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// MOVPRFX Zresult, Zop1; AND Zresult.D, Pg/M, Zresult.D, Zop2.D + /// svint64_t svand[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2) + /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// AND Ztied2.D, Pg/M, Ztied2.D, Zop1.D + /// AND Zresult.D, Zop1.D, Zop2.D + /// svint64_t svand[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) + /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; AND Zresult.D, Pg/M, Zresult.D, Zop2.D + /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; AND Zresult.D, Pg/M, Zresult.D, Zop1.D + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) => And(left, right); + + /// + /// svint8_t svand[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2) + /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// MOVPRFX Zresult, Zop1; AND Zresult.B, Pg/M, Zresult.B, Zop2.B + /// svint8_t svand[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2) + /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// AND Ztied2.B, Pg/M, Ztied2.B, Zop1.B + /// AND Zresult.D, Zop1.D, Zop2.D + /// svint8_t svand[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) + /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; AND Zresult.B, Pg/M, Zresult.B, Zop2.B + /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; AND Zresult.B, Pg/M, Zresult.B, Zop1.B + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) => And(left, right); + + /// + /// svuint16_t svand[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// MOVPRFX Zresult, Zop1; AND Zresult.H, Pg/M, Zresult.H, Zop2.H + /// svuint16_t svand[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// AND Ztied2.H, Pg/M, Ztied2.H, Zop1.H + /// AND Zresult.D, Zop1.D, Zop2.D + /// svuint16_t svand[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; AND Zresult.H, Pg/M, Zresult.H, Zop2.H + /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; AND Zresult.H, Pg/M, Zresult.H, Zop1.H + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) => And(left, right); + + /// + /// svuint32_t svand[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// MOVPRFX Zresult, Zop1; AND Zresult.S, Pg/M, Zresult.S, Zop2.S + /// svuint32_t svand[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// AND Ztied2.S, Pg/M, Ztied2.S, Zop1.S + /// AND Zresult.D, Zop1.D, Zop2.D + /// svuint32_t svand[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; AND Zresult.S, Pg/M, Zresult.S, Zop2.S + /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; AND Zresult.S, Pg/M, Zresult.S, Zop1.S + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) => And(left, right); + + /// + /// svuint64_t svand[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// MOVPRFX Zresult, Zop1; AND Zresult.D, Pg/M, Zresult.D, Zop2.D + /// svuint64_t svand[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// AND Ztied2.D, Pg/M, Ztied2.D, Zop1.D + /// AND Zresult.D, Zop1.D, Zop2.D + /// svuint64_t svand[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; AND Zresult.D, Pg/M, Zresult.D, Zop2.D + /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; AND Zresult.D, Pg/M, Zresult.D, Zop1.D + /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector And(Vector left, Vector right) => And(left, right); + + + /// AndAcross : Bitwise AND reduction to scalar + + /// + /// uint8_t svandv[_u8](svbool_t pg, svuint8_t op) + /// ANDV Bresult, Pg, Zop.B + /// + public static unsafe Vector AndAcross(Vector value) => AndAcross(value); + + /// + /// int16_t svandv[_s16](svbool_t pg, svint16_t op) + /// ANDV Hresult, Pg, Zop.H + /// + public static unsafe Vector AndAcross(Vector value) => AndAcross(value); + + /// + /// int32_t svandv[_s32](svbool_t pg, svint32_t op) + /// ANDV Sresult, Pg, Zop.S + /// + public static unsafe Vector AndAcross(Vector value) => AndAcross(value); + + /// + /// int64_t svandv[_s64](svbool_t pg, svint64_t op) + /// ANDV Dresult, Pg, Zop.D + /// + public static unsafe Vector AndAcross(Vector value) => AndAcross(value); + + /// + /// int8_t svandv[_s8](svbool_t pg, svint8_t op) + /// ANDV Bresult, Pg, Zop.B + /// + public static unsafe Vector AndAcross(Vector value) => AndAcross(value); + + /// + /// uint16_t svandv[_u16](svbool_t pg, svuint16_t op) + /// ANDV Hresult, Pg, Zop.H + /// + public static unsafe Vector AndAcross(Vector value) => AndAcross(value); + + /// + /// uint32_t svandv[_u32](svbool_t pg, svuint32_t op) + /// ANDV Sresult, Pg, Zop.S + /// + public static unsafe Vector AndAcross(Vector value) => AndAcross(value); + + /// + /// uint64_t svandv[_u64](svbool_t pg, svuint64_t op) + /// ANDV Dresult, Pg, Zop.D + /// + public static unsafe Vector AndAcross(Vector value) => AndAcross(value); + + /// ConditionalSelect : Conditionally select elements /// @@ -1128,6 +1310,189 @@ internal Arm64() { } /// public static unsafe Vector Multiply(Vector left, Vector right) => Multiply(left, right); + + /// Or : Bitwise inclusive OR + + /// + /// svuint8_t svorr[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// MOVPRFX Zresult, Zop1; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// svuint8_t svorr[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// ORR Ztied2.B, Pg/M, Ztied2.B, Zop1.B + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svuint8_t svorr[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; ORR Zresult.B, Pg/M, Zresult.B, Zop1.B + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) => Or(left, right); + + /// + /// svint16_t svorr[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2) + /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// MOVPRFX Zresult, Zop1; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// svint16_t svorr[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2) + /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// ORR Ztied2.H, Pg/M, Ztied2.H, Zop1.H + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svint16_t svorr[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) + /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; ORR Zresult.H, Pg/M, Zresult.H, Zop1.H + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) => Or(left, right); + + /// + /// svint32_t svorr[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2) + /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// MOVPRFX Zresult, Zop1; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// svint32_t svorr[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2) + /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// ORR Ztied2.S, Pg/M, Ztied2.S, Zop1.S + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svint32_t svorr[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) + /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; ORR Zresult.S, Pg/M, Zresult.S, Zop1.S + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) => Or(left, right); + + /// + /// svint64_t svorr[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2) + /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// MOVPRFX Zresult, Zop1; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// svint64_t svorr[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2) + /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// ORR Ztied2.D, Pg/M, Ztied2.D, Zop1.D + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svint64_t svorr[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) + /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; ORR Zresult.D, Pg/M, Zresult.D, Zop1.D + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) => Or(left, right); + + /// + /// svint8_t svorr[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2) + /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// MOVPRFX Zresult, Zop1; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// svint8_t svorr[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2) + /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// ORR Ztied2.B, Pg/M, Ztied2.B, Zop1.B + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svint8_t svorr[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) + /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; ORR Zresult.B, Pg/M, Zresult.B, Zop1.B + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) => Or(left, right); + + /// + /// svuint16_t svorr[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// MOVPRFX Zresult, Zop1; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// svuint16_t svorr[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// ORR Ztied2.H, Pg/M, Ztied2.H, Zop1.H + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svuint16_t svorr[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; ORR Zresult.H, Pg/M, Zresult.H, Zop1.H + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) => Or(left, right); + + /// + /// svuint32_t svorr[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// MOVPRFX Zresult, Zop1; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// svuint32_t svorr[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// ORR Ztied2.S, Pg/M, Ztied2.S, Zop1.S + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svuint32_t svorr[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; ORR Zresult.S, Pg/M, Zresult.S, Zop1.S + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) => Or(left, right); + + /// + /// svuint64_t svorr[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// MOVPRFX Zresult, Zop1; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// svuint64_t svorr[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// ORR Ztied2.D, Pg/M, Ztied2.D, Zop1.D + /// ORR Zresult.D, Zop1.D, Zop2.D + /// svuint64_t svorr[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; ORR Zresult.D, Pg/M, Zresult.D, Zop1.D + /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Or(Vector left, Vector right) => Or(left, right); + + + /// OrAcross : Bitwise inclusive OR reduction to scalar + + /// + /// uint8_t svorv[_u8](svbool_t pg, svuint8_t op) + /// ORV Bresult, Pg, Zop.B + /// + public static unsafe Vector OrAcross(Vector value) => OrAcross(value); + + /// + /// int16_t svorv[_s16](svbool_t pg, svint16_t op) + /// ORV Hresult, Pg, Zop.H + /// + public static unsafe Vector OrAcross(Vector value) => OrAcross(value); + + /// + /// int32_t svorv[_s32](svbool_t pg, svint32_t op) + /// ORV Sresult, Pg, Zop.S + /// + public static unsafe Vector OrAcross(Vector value) => OrAcross(value); + + /// + /// int64_t svorv[_s64](svbool_t pg, svint64_t op) + /// ORV Dresult, Pg, Zop.D + /// + public static unsafe Vector OrAcross(Vector value) => OrAcross(value); + + /// + /// int8_t svorv[_s8](svbool_t pg, svint8_t op) + /// ORV Bresult, Pg, Zop.B + /// + public static unsafe Vector OrAcross(Vector value) => OrAcross(value); + + /// + /// uint16_t svorv[_u16](svbool_t pg, svuint16_t op) + /// ORV Hresult, Pg, Zop.H + /// + public static unsafe Vector OrAcross(Vector value) => OrAcross(value); + + /// + /// uint32_t svorv[_u32](svbool_t pg, svuint32_t op) + /// ORV Sresult, Pg, Zop.S + /// + public static unsafe Vector OrAcross(Vector value) => OrAcross(value); + + /// + /// uint64_t svorv[_u64](svbool_t pg, svuint64_t op) + /// ORV Dresult, Pg, Zop.D + /// + public static unsafe Vector OrAcross(Vector value) => OrAcross(value); + + /// SignExtend16 : Sign-extend the low 16 bits /// @@ -1514,6 +1879,189 @@ internal Arm64() { } /// public static unsafe Vector UnzipOdd(Vector left, Vector right) => UnzipOdd(left, right); + + /// Xor : Bitwise exclusive OR + + /// + /// svuint8_t sveor[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// MOVPRFX Zresult, Zop1; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// svuint8_t sveor[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// EOR Ztied2.B, Pg/M, Ztied2.B, Zop1.B + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svuint8_t sveor[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; EOR Zresult.B, Pg/M, Zresult.B, Zop1.B + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) => Xor(left, right); + + /// + /// svint16_t sveor[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2) + /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// MOVPRFX Zresult, Zop1; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// svint16_t sveor[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2) + /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// EOR Ztied2.H, Pg/M, Ztied2.H, Zop1.H + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svint16_t sveor[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) + /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; EOR Zresult.H, Pg/M, Zresult.H, Zop1.H + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) => Xor(left, right); + + /// + /// svint32_t sveor[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2) + /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// MOVPRFX Zresult, Zop1; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// svint32_t sveor[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2) + /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// EOR Ztied2.S, Pg/M, Ztied2.S, Zop1.S + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svint32_t sveor[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) + /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; EOR Zresult.S, Pg/M, Zresult.S, Zop1.S + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) => Xor(left, right); + + /// + /// svint64_t sveor[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2) + /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// MOVPRFX Zresult, Zop1; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// svint64_t sveor[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2) + /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// EOR Ztied2.D, Pg/M, Ztied2.D, Zop1.D + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svint64_t sveor[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) + /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; EOR Zresult.D, Pg/M, Zresult.D, Zop1.D + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) => Xor(left, right); + + /// + /// svint8_t sveor[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2) + /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// MOVPRFX Zresult, Zop1; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// svint8_t sveor[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2) + /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B + /// EOR Ztied2.B, Pg/M, Ztied2.B, Zop1.B + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svint8_t sveor[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) + /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B + /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; EOR Zresult.B, Pg/M, Zresult.B, Zop1.B + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) => Xor(left, right); + + /// + /// svuint16_t sveor[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// MOVPRFX Zresult, Zop1; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// svuint16_t sveor[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H + /// EOR Ztied2.H, Pg/M, Ztied2.H, Zop1.H + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svuint16_t sveor[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H + /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; EOR Zresult.H, Pg/M, Zresult.H, Zop1.H + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) => Xor(left, right); + + /// + /// svuint32_t sveor[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// MOVPRFX Zresult, Zop1; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// svuint32_t sveor[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S + /// EOR Ztied2.S, Pg/M, Ztied2.S, Zop1.S + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svuint32_t sveor[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S + /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; EOR Zresult.S, Pg/M, Zresult.S, Zop1.S + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) => Xor(left, right); + + /// + /// svuint64_t sveor[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// MOVPRFX Zresult, Zop1; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// svuint64_t sveor[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D + /// EOR Ztied2.D, Pg/M, Ztied2.D, Zop1.D + /// EOR Zresult.D, Zop1.D, Zop2.D + /// svuint64_t sveor[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D + /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; EOR Zresult.D, Pg/M, Zresult.D, Zop1.D + /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static unsafe Vector Xor(Vector left, Vector right) => Xor(left, right); + + + /// XorAcross : Bitwise exclusive OR reduction to scalar + + /// + /// uint8_t sveorv[_u8](svbool_t pg, svuint8_t op) + /// EORV Bresult, Pg, Zop.B + /// + public static unsafe Vector XorAcross(Vector value) => XorAcross(value); + + /// + /// int16_t sveorv[_s16](svbool_t pg, svint16_t op) + /// EORV Hresult, Pg, Zop.H + /// + public static unsafe Vector XorAcross(Vector value) => XorAcross(value); + + /// + /// int32_t sveorv[_s32](svbool_t pg, svint32_t op) + /// EORV Sresult, Pg, Zop.S + /// + public static unsafe Vector XorAcross(Vector value) => XorAcross(value); + + /// + /// int64_t sveorv[_s64](svbool_t pg, svint64_t op) + /// EORV Dresult, Pg, Zop.D + /// + public static unsafe Vector XorAcross(Vector value) => XorAcross(value); + + /// + /// int8_t sveorv[_s8](svbool_t pg, svint8_t op) + /// EORV Bresult, Pg, Zop.B + /// + public static unsafe Vector XorAcross(Vector value) => XorAcross(value); + + /// + /// uint16_t sveorv[_u16](svbool_t pg, svuint16_t op) + /// EORV Hresult, Pg, Zop.H + /// + public static unsafe Vector XorAcross(Vector value) => XorAcross(value); + + /// + /// uint32_t sveorv[_u32](svbool_t pg, svuint32_t op) + /// EORV Sresult, Pg, Zop.S + /// + public static unsafe Vector XorAcross(Vector value) => XorAcross(value); + + /// + /// uint64_t sveorv[_u64](svbool_t pg, svuint64_t op) + /// EORV Dresult, Pg, Zop.D + /// + public static unsafe Vector XorAcross(Vector value) => XorAcross(value); + + /// ZeroExtend16 : Zero-extend the low 16 bits /// diff --git a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs index 1262604f92895..22215ff51a80c 100644 --- a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs +++ b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs @@ -4197,6 +4197,25 @@ internal Arm64() { } public static System.Numerics.Vector AddAcross(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector AddAcross(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector AddAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } + + public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + + public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } + public static ulong Count16BitElements([ConstantExpected] SveMaskPattern pattern = SveMaskPattern.All) { throw null; } public static ulong Count32BitElements([ConstantExpected] SveMaskPattern pattern = SveMaskPattern.All) { throw null; } public static ulong Count64BitElements([ConstantExpected] SveMaskPattern pattern = SveMaskPattern.All) { throw null; } @@ -4290,6 +4309,24 @@ internal Arm64() { } public static unsafe System.Numerics.Vector LoadVectorUInt32ZeroExtendToInt64(System.Numerics.Vector mask, uint* address) { throw null; } public static unsafe System.Numerics.Vector LoadVectorUInt32ZeroExtendToUInt64(System.Numerics.Vector mask, uint* address) { throw null; } + public static System.Numerics.Vector Or(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Or(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Or(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Or(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Or(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Or(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Or(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Or(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + + public static System.Numerics.Vector OrAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector OrAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector OrAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector OrAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector OrAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector OrAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector OrAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector OrAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector SignExtend16(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector SignExtend16(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector SignExtend32(System.Numerics.Vector value) { throw null; } @@ -4348,6 +4385,24 @@ internal Arm64() { } public static System.Numerics.Vector UnzipOdd(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } public static System.Numerics.Vector UnzipOdd(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Xor(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Xor(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Xor(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Xor(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Xor(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Xor(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Xor(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector Xor(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + + public static System.Numerics.Vector XorAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector XorAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector XorAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector XorAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector XorAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector XorAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector XorAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector XorAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector ZeroExtend16(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector ZeroExtend16(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector ZeroExtend32(System.Numerics.Vector value) { throw null; } diff --git a/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs b/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs index 9b76978229562..0713ac24af211 100644 --- a/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs +++ b/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs @@ -2921,6 +2921,24 @@ ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_AddAcross_ulong_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AddAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["ValidateReduceOpResult"] = "Helpers.AddAcrossWidening(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_AddAcross_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AddAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["ValidateReduceOpResult"] = "Helpers.AddAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_And_sbyte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "And", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "(sbyte)TestLibrary.Generator.GetSByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetSByte()", ["ValidateIterResult"] = "Helpers.And(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.And(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_And_short", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "And", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "(short)TestLibrary.Generator.GetInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt16()", ["ValidateIterResult"] = "Helpers.And(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.And(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_And_int", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "And", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt32()", ["ValidateIterResult"] = "Helpers.And(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.And(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_And_long", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "And", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt64()", ["ValidateIterResult"] = "Helpers.And(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.And(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_And_byte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "And", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Byte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "(byte)TestLibrary.Generator.GetByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetByte()", ["ValidateIterResult"] = "Helpers.And(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.And(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_And_ushort", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "And", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt16()", ["ValidateIterResult"] = "Helpers.And(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.And(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_And_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "And", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt32()", ["ValidateIterResult"] = "Helpers.And(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.And(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_And_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "And", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt64()", ["ValidateIterResult"] = "Helpers.And(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.And(left[i], right[i])"}), + + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_AndAcross_sbyte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSByte()", ["ValidateReduceOpResult"] = "Helpers.AndAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_AndAcross_short", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt16()", ["ValidateReduceOpResult"] = "Helpers.AndAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_AndAcross_int", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["ValidateReduceOpResult"] = "Helpers.AndAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_AndAcross_long", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["ValidateReduceOpResult"] = "Helpers.AndAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_AndAcross_byte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Byte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetByte()", ["ValidateReduceOpResult"] = "Helpers.AndAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_AndAcross_ushort", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt16()", ["ValidateReduceOpResult"] = "Helpers.AndAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_AndAcross_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["ValidateReduceOpResult"] = "Helpers.AndAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_AndAcross_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["ValidateReduceOpResult"] = "Helpers.AndAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveConditionalSelect.template", new Dictionary { ["TestName"] = "Sve_ConditionalSelect_float", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "ConditionalSelect", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Single", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Single", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Single", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "Single", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSingle()", ["NextValueOp2"] = "TestLibrary.Generator.GetSingle()", ["NextValueOp3"] = "TestLibrary.Generator.GetSingle()", ["ValidateIterResult"] = "(firstOp[i] != 0 ? (result[i] != secondOp[i]) : (result[i] != thirdOp[i]))",}), ("SveConditionalSelect.template", new Dictionary { ["TestName"] = "Sve_ConditionalSelect_double", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "ConditionalSelect", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Double", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Double", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Double", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "Double", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetDouble()", ["NextValueOp2"] = "TestLibrary.Generator.GetDouble()", ["NextValueOp3"] = "TestLibrary.Generator.GetDouble()", ["ValidateIterResult"] = "(firstOp[i] != 0 ? (result[i] != secondOp[i]) : (result[i] != thirdOp[i]))",}), ("SveConditionalSelect.template", new Dictionary { ["TestName"] = "Sve_ConditionalSelect_sbyte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "ConditionalSelect", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "SByte", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetSByte()", ["NextValueOp3"] = "TestLibrary.Generator.GetSByte()", ["ValidateIterResult"] = "(firstOp[i] != 0 ? (result[i] != secondOp[i]) : (result[i] != thirdOp[i]))",}), @@ -3020,6 +3038,24 @@ ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Multiply_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Multiply", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt32()", ["ValidateIterResult"] = "Helpers.Multiply(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Multiply(left[i], right[i])"}), ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Multiply_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Multiply", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt64()", ["ValidateIterResult"] = "Helpers.Multiply(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Multiply(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Or_sbyte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Or", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "(sbyte)TestLibrary.Generator.GetSByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetSByte()", ["ValidateIterResult"] = "Helpers.Or(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Or(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Or_short", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Or", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "(short)TestLibrary.Generator.GetInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt16()", ["ValidateIterResult"] = "Helpers.Or(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Or(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Or_int", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Or", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt32()", ["ValidateIterResult"] = "Helpers.Or(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Or(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Or_long", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Or", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt64()", ["ValidateIterResult"] = "Helpers.Or(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Or(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Or_byte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Or", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Byte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "(byte)TestLibrary.Generator.GetByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetByte()", ["ValidateIterResult"] = "Helpers.Or(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Or(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Or_ushort", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Or", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt16()", ["ValidateIterResult"] = "Helpers.Or(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Or(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Or_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Or", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt32()", ["ValidateIterResult"] = "Helpers.Or(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Or(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Or_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Or", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt64()", ["ValidateIterResult"] = "Helpers.Or(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Or(left[i], right[i])"}), + + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_OrAcross_sbyte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSByte()", ["ValidateReduceOpResult"] = "Helpers.OrAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_OrAcross_short", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt16()", ["ValidateReduceOpResult"] = "Helpers.OrAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_OrAcross_int", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["ValidateReduceOpResult"] = "Helpers.OrAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_OrAcross_long", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["ValidateReduceOpResult"] = "Helpers.OrAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_OrAcross_byte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Byte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetByte()", ["ValidateReduceOpResult"] = "Helpers.OrAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_OrAcross_ushort", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt16()", ["ValidateReduceOpResult"] = "Helpers.OrAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_OrAcross_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["ValidateReduceOpResult"] = "Helpers.OrAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_OrAcross_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["ValidateReduceOpResult"] = "Helpers.OrAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveSimpleVecOpTest.template", new Dictionary { ["TestName"] = "Sve_SignExtend16_int", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "SignExtend16", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["ValidateIterResult"] = "result[i] != Helpers.SignExtend(firstOp[i], 16, false)", ["GetIterResult"] = "Helpers.SignExtend(leftOp[i], 16, false)"}), ("SveSimpleVecOpTest.template", new Dictionary { ["TestName"] = "Sve_SignExtend16_long", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "SignExtend16", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["ValidateIterResult"] = "result[i] != Helpers.SignExtend(firstOp[i], 16, false)", ["GetIterResult"] = "Helpers.SignExtend(leftOp[i], 16, false)"}), ("SveSimpleVecOpTest.template", new Dictionary { ["TestName"] = "Sve_SignExtend32_long", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "SignExtend32", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["ValidateIterResult"] = "result[i] != Helpers.SignExtend(firstOp[i], 32, false)", ["GetIterResult"] = "Helpers.SignExtend(leftOp[i], 32, false)"}), @@ -3045,6 +3081,24 @@ ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Subtract_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Subtract", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt32()", ["ValidateIterResult"] = "Helpers.Subtract(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Subtract(left[i], right[i])"}), ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Subtract_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Subtract", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt64()", ["ValidateIterResult"] = "Helpers.Subtract(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Subtract(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Xor_sbyte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Xor", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "(sbyte)TestLibrary.Generator.GetSByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetSByte()", ["ValidateIterResult"] = "Helpers.Xor(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Xor(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Xor_short", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Xor", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "(short)TestLibrary.Generator.GetInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt16()", ["ValidateIterResult"] = "Helpers.Xor(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Xor(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Xor_int", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Xor", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt32()", ["ValidateIterResult"] = "Helpers.Xor(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Xor(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Xor_long", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Xor", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt64()", ["ValidateIterResult"] = "Helpers.Xor(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Xor(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Xor_byte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Xor", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Byte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "(byte)TestLibrary.Generator.GetByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetByte()", ["ValidateIterResult"] = "Helpers.Xor(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Xor(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Xor_ushort", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Xor", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt16()", ["ValidateIterResult"] = "Helpers.Xor(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Xor(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Xor_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Xor", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt32()", ["ValidateIterResult"] = "Helpers.Xor(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Xor(left[i], right[i])"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_Xor_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Xor", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt64()", ["ValidateIterResult"] = "Helpers.Xor(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.Xor(left[i], right[i])"}), + + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_XorAcross_sbyte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "XorAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSByte()", ["ValidateReduceOpResult"] = "Helpers.XorAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_XorAcross_short", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "XorAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt16()", ["ValidateReduceOpResult"] = "Helpers.XorAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_XorAcross_int", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "XorAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["ValidateReduceOpResult"] = "Helpers.XorAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_XorAcross_long", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "XorAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["ValidateReduceOpResult"] = "Helpers.XorAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_XorAcross_byte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "XorAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Byte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetByte()", ["ValidateReduceOpResult"] = "Helpers.XorAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_XorAcross_ushort", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "XorAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt16()", ["ValidateReduceOpResult"] = "Helpers.XorAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_XorAcross_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "XorAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["ValidateReduceOpResult"] = "Helpers.XorAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_XorAcross_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "XorAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["ValidateReduceOpResult"] = "Helpers.XorAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecPairBinOpTest.template", new Dictionary { ["TestName"] = "SveUnzipEven_float", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "UnzipEven", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Single", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Single", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Single", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSingle()", ["NextValueOp2"] = "TestLibrary.Generator.GetSingle()", ["ValidateEntry"] = "result[index] != left[i] || result[index + half] != right[i]"}), ("SveVecPairBinOpTest.template", new Dictionary { ["TestName"] = "SveUnzipEven_double", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "UnzipEven", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Double", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Double", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Double", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetDouble()", ["NextValueOp2"] = "TestLibrary.Generator.GetDouble()", ["ValidateEntry"] = "result[index] != left[i] || result[index + half] != right[i]"}), ("SveVecPairBinOpTest.template", new Dictionary { ["TestName"] = "SveUnzipEven_sbyte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "UnzipEven", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetSByte()", ["ValidateEntry"] = "result[index] != left[i] || result[index + half] != right[i]"}), diff --git a/src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs b/src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs index f8c8673296911..faf6d504ece6b 100644 --- a/src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs +++ b/src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs @@ -5118,10 +5118,16 @@ private static double Pairwise(Func pairOp, double[] op1 public static sbyte AddAcross(sbyte[] op1) => Reduce(Add, op1); + public static sbyte AndAcross(sbyte[] op1) => Reduce(And, op1); + public static sbyte MaxAcross(sbyte[] op1) => Reduce(Max, op1); public static sbyte MinAcross(sbyte[] op1) => Reduce(Min, op1); + public static sbyte OrAcross(sbyte[] op1) => Reduce(Or, op1); + + public static sbyte XorAcross(sbyte[] op1) => Reduce(Xor, op1); + private static sbyte Reduce(Func reduceOp, sbyte[] op1) { sbyte acc = op1[0]; @@ -5136,10 +5142,16 @@ private static sbyte Reduce(Func reduceOp, sbyte[] op1) public static byte AddAcross(byte[] op1) => Reduce(Add, op1); + public static byte AndAcross(byte[] op1) => Reduce(And, op1); + public static byte MaxAcross(byte[] op1) => Reduce(Max, op1); public static byte MinAcross(byte[] op1) => Reduce(Min, op1); + public static byte OrAcross(byte[] op1) => Reduce(Or, op1); + + public static byte XorAcross(byte[] op1) => Reduce(Xor, op1); + private static byte Reduce(Func reduceOp, byte[] op1) { byte acc = op1[0]; @@ -5154,10 +5166,16 @@ private static byte Reduce(Func reduceOp, byte[] op1) public static short AddAcross(short[] op1) => Reduce(Add, op1); + public static short AndAcross(short[] op1) => Reduce(And, op1); + public static short MaxAcross(short[] op1) => Reduce(Max, op1); public static short MinAcross(short[] op1) => Reduce(Min, op1); + public static short OrAcross(short[] op1) => Reduce(Or, op1); + + public static short XorAcross(short[] op1) => Reduce(Xor, op1); + private static short Reduce(Func reduceOp, short[] op1) { short acc = op1[0]; @@ -5172,10 +5190,16 @@ private static short Reduce(Func reduceOp, short[] op1) public static ushort AddAcross(ushort[] op1) => Reduce(Add, op1); + public static ushort AndAcross(ushort[] op1) => Reduce(And, op1); + public static ushort MaxAcross(ushort[] op1) => Reduce(Max, op1); public static ushort MinAcross(ushort[] op1) => Reduce(Min, op1); + public static ushort OrAcross(ushort[] op1) => Reduce(Or, op1); + + public static ushort XorAcross(ushort[] op1) => Reduce(Xor, op1); + private static ushort Reduce(Func reduceOp, ushort[] op1) { ushort acc = op1[0]; @@ -5190,10 +5214,16 @@ private static ushort Reduce(Func reduceOp, ushort[] op1 public static int AddAcross(int[] op1) => Reduce(Add, op1); + public static int AndAcross(int[] op1) => Reduce(And, op1); + public static int MaxAcross(int[] op1) => Reduce(Max, op1); public static int MinAcross(int[] op1) => Reduce(Min, op1); + public static int OrAcross(int[] op1) => Reduce(Or, op1); + + public static int XorAcross(int[] op1) => Reduce(Xor, op1); + private static int Reduce(Func reduceOp, int[] op1) { int acc = op1[0]; @@ -5208,10 +5238,16 @@ private static int Reduce(Func reduceOp, int[] op1) public static uint AddAcross(uint[] op1) => Reduce(Add, op1); + public static uint AndAcross(uint[] op1) => Reduce(And, op1); + public static uint MaxAcross(uint[] op1) => Reduce(Max, op1); public static uint MinAcross(uint[] op1) => Reduce(Min, op1); + public static uint OrAcross(uint[] op1) => Reduce(Or, op1); + + public static uint XorAcross(uint[] op1) => Reduce(Xor, op1); + private static uint Reduce(Func reduceOp, uint[] op1) { uint acc = op1[0]; @@ -5226,10 +5262,16 @@ private static uint Reduce(Func reduceOp, uint[] op1) public static long AddAcross(long[] op1) => Reduce(Add, op1); + public static long AndAcross(long[] op1) => Reduce(And, op1); + public static long MaxAcross(long[] op1) => Reduce(Max, op1); public static long MinAcross(long[] op1) => Reduce(Min, op1); + public static long OrAcross(long[] op1) => Reduce(Or, op1); + + public static long XorAcross(long[] op1) => Reduce(Xor, op1); + private static long Reduce(Func reduceOp, long[] op1) { long acc = op1[0]; @@ -5244,10 +5286,16 @@ private static long Reduce(Func reduceOp, long[] op1) public static ulong AddAcross(ulong[] op1) => Reduce(Add, op1); + public static ulong AndAcross(ulong[] op1) => Reduce(And, op1); + public static ulong MaxAcross(ulong[] op1) => Reduce(Max, op1); public static ulong MinAcross(ulong[] op1) => Reduce(Min, op1); + public static ulong OrAcross(ulong[] op1) => Reduce(Or, op1); + + public static ulong XorAcross(ulong[] op1) => Reduce(Xor, op1); + private static ulong Reduce(Func reduceOp, ulong[] op1) { ulong acc = op1[0]; From f31225744db607a2987f107fdc6673902108037f Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Thu, 2 May 2024 09:58:20 +0100 Subject: [PATCH 2/5] Fix fadda --- src/coreclr/jit/codegenarm64test.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/coreclr/jit/codegenarm64test.cpp b/src/coreclr/jit/codegenarm64test.cpp index 7fda65ddc6aee..a588b0e927246 100644 --- a/src/coreclr/jit/codegenarm64test.cpp +++ b/src/coreclr/jit/codegenarm64test.cpp @@ -5116,11 +5116,11 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_H); // FMINP ., /M, ., . // IF_SVE_HJ_3A - theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_2BYTE, REG_V21, REG_P6, REG_V14, + theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_SCALABLE, REG_V21, REG_P6, REG_V14, INS_OPTS_SCALABLE_H); // FADDA , , , . - theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_4BYTE, REG_V22, REG_P5, REG_V13, + theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_SCALABLE, REG_V22, REG_P5, REG_V13, INS_OPTS_SCALABLE_S); // FADDA , , , . - theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_8BYTE, REG_V23, REG_P4, REG_V12, + theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_SCALABLE, REG_V23, REG_P4, REG_V12, INS_OPTS_SCALABLE_D); // FADDA , , , . // IF_SVE_HL_3A From f26f7cee2e5774cc4cd7d5db657156dce3913d54 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Thu, 2 May 2024 11:44:16 +0100 Subject: [PATCH 3/5] Fix unpkh/fexpa/frecpe --- src/coreclr/jit/codegenarm64test.cpp | 2 +- src/coreclr/jit/emitarm64sve.cpp | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/codegenarm64test.cpp b/src/coreclr/jit/codegenarm64test.cpp index a588b0e927246..bde167fc05a9e 100644 --- a/src/coreclr/jit/codegenarm64test.cpp +++ b/src/coreclr/jit/codegenarm64test.cpp @@ -8909,7 +8909,7 @@ void CodeGen::genArm64EmitterUnitTestsSve() // SUNPKLO ., . theEmitter->emitIns_R_R(INS_sve_sunpklo, EA_SCALABLE, REG_V1, REG_V5, INS_OPTS_SCALABLE_S); // UUNPKHI ., . - theEmitter->emitIns_R_R(INS_sve_uunpkhi, EA_SCALABLE, REG_V5, REG_V1, INS_OPTS_SCALABLE_D); + theEmitter->emitIns_R_R(INS_sve_uunpkhi, EA_SCALABLE, REG_V5, REG_V1, INS_OPTS_SCALABLE_B); // UUNPKLO ., . theEmitter->emitIns_R_R(INS_sve_uunpklo, EA_SCALABLE, REG_V8, REG_V6, INS_OPTS_SCALABLE_S); diff --git a/src/coreclr/jit/emitarm64sve.cpp b/src/coreclr/jit/emitarm64sve.cpp index 2ac4d73b2c018..9392aec6376df 100644 --- a/src/coreclr/jit/emitarm64sve.cpp +++ b/src/coreclr/jit/emitarm64sve.cpp @@ -11823,6 +11823,7 @@ BYTE* emitter::emitOutput_InstrSve(BYTE* dst, instrDesc* id) code |= insEncodeSveElemsize(optGetSveElemsize((insOpts)(id->idInsOpt() + 1))); // xx dst += emitOutput_Instr(dst, code); break; + case IF_SVE_BF_2A: // ........xx.xxiii ......nnnnnddddd -- SVE bitwise shift by immediate (unpredicated) case IF_SVE_FT_2A: // ........xx.xxiii ......nnnnnddddd -- SVE2 bitwise shift and insert case IF_SVE_FU_2A: // ........xx.xxiii ......nnnnnddddd -- SVE2 bitwise shift right and accumulate @@ -14396,8 +14397,13 @@ void emitter::emitInsSveSanityCheck(instrDesc* id) break; case IF_SVE_BJ_2A: // ........xx...... ......nnnnnddddd -- SVE floating-point exponential accelerator - case IF_SVE_CH_2A: // ........xx...... ......nnnnnddddd -- SVE unpack vector elements case IF_SVE_HF_2A: // ........xx...... ......nnnnnddddd -- SVE floating-point reciprocal estimate (unpredicated) + assert(insOptsScalableAtLeastHalf(id->idInsOpt())); + assert(isVectorRegister(id->idReg1())); + assert(isVectorRegister(id->idReg2())); + break; + + case IF_SVE_CH_2A: // ........xx...... ......nnnnnddddd -- SVE unpack vector elements assert(insOptsScalableWide(id->idInsOpt())); assert(isVectorRegister(id->idReg1())); assert(isVectorRegister(id->idReg2())); From 7a23e958bbcdab03b5b80ab5b6c2df04ede901b2 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Thu, 2 May 2024 11:47:40 +0100 Subject: [PATCH 4/5] Reorder System.Runtime.Intrinsics.cs --- .../ref/System.Runtime.Intrinsics.cs | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs index 22215ff51a80c..dee510b5c22eb 100644 --- a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs +++ b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs @@ -4197,8 +4197,6 @@ internal Arm64() { } public static System.Numerics.Vector AddAcross(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector AddAcross(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector AddAcross(System.Numerics.Vector value) { throw null; } - public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } - public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } @@ -4207,8 +4205,9 @@ internal Arm64() { } public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } - public static System.Numerics.Vector And(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } From 8a9255680f5f46e4e80f5040cb1fb104cd04d2f6 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Thu, 2 May 2024 17:16:11 +0100 Subject: [PATCH 5/5] Fix API head comments --- .../Arm/Sve.PlatformNotSupported.cs | 168 +++--------------- .../src/System/Runtime/Intrinsics/Arm/Sve.cs | 168 +++--------------- 2 files changed, 48 insertions(+), 288 deletions(-) diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs index 14c4274a7aaf4..b4f28f01193ea 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs @@ -215,15 +215,10 @@ internal Arm64() { } /// /// svuint8_t svand[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2) - /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// MOVPRFX Zresult, Zop1; AND Zresult.B, Pg/M, Zresult.B, Zop2.B /// svuint8_t svand[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// svuint8_t svand[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// AND Ztied2.B, Pg/M, Ztied2.B, Zop1.B /// AND Zresult.D, Zop1.D, Zop2.D - /// svuint8_t svand[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) - /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; AND Zresult.B, Pg/M, Zresult.B, Zop2.B - /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; AND Zresult.B, Pg/M, Zresult.B, Zop1.B /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -231,15 +226,10 @@ internal Arm64() { } /// /// svint16_t svand[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2) - /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// MOVPRFX Zresult, Zop1; AND Zresult.H, Pg/M, Zresult.H, Zop2.H /// svint16_t svand[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2) + /// svint16_t svand[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// AND Ztied2.H, Pg/M, Ztied2.H, Zop1.H /// AND Zresult.D, Zop1.D, Zop2.D - /// svint16_t svand[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) - /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; AND Zresult.H, Pg/M, Zresult.H, Zop2.H - /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; AND Zresult.H, Pg/M, Zresult.H, Zop1.H /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -247,15 +237,10 @@ internal Arm64() { } /// /// svint32_t svand[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2) - /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// MOVPRFX Zresult, Zop1; AND Zresult.S, Pg/M, Zresult.S, Zop2.S /// svint32_t svand[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2) + /// svint32_t svand[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// AND Ztied2.S, Pg/M, Ztied2.S, Zop1.S /// AND Zresult.D, Zop1.D, Zop2.D - /// svint32_t svand[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) - /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; AND Zresult.S, Pg/M, Zresult.S, Zop2.S - /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; AND Zresult.S, Pg/M, Zresult.S, Zop1.S /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -263,15 +248,10 @@ internal Arm64() { } /// /// svint64_t svand[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2) - /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// MOVPRFX Zresult, Zop1; AND Zresult.D, Pg/M, Zresult.D, Zop2.D /// svint64_t svand[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2) + /// svint64_t svand[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// AND Ztied2.D, Pg/M, Ztied2.D, Zop1.D /// AND Zresult.D, Zop1.D, Zop2.D - /// svint64_t svand[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) - /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; AND Zresult.D, Pg/M, Zresult.D, Zop2.D - /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; AND Zresult.D, Pg/M, Zresult.D, Zop1.D /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -279,15 +259,10 @@ internal Arm64() { } /// /// svint8_t svand[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2) - /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// MOVPRFX Zresult, Zop1; AND Zresult.B, Pg/M, Zresult.B, Zop2.B /// svint8_t svand[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2) + /// svint8_t svand[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// AND Ztied2.B, Pg/M, Ztied2.B, Zop1.B /// AND Zresult.D, Zop1.D, Zop2.D - /// svint8_t svand[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) - /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; AND Zresult.B, Pg/M, Zresult.B, Zop2.B - /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; AND Zresult.B, Pg/M, Zresult.B, Zop1.B /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -295,15 +270,10 @@ internal Arm64() { } /// /// svuint16_t svand[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2) - /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// MOVPRFX Zresult, Zop1; AND Zresult.H, Pg/M, Zresult.H, Zop2.H /// svuint16_t svand[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// svuint16_t svand[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// AND Ztied2.H, Pg/M, Ztied2.H, Zop1.H /// AND Zresult.D, Zop1.D, Zop2.D - /// svuint16_t svand[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) - /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; AND Zresult.H, Pg/M, Zresult.H, Zop2.H - /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; AND Zresult.H, Pg/M, Zresult.H, Zop1.H /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -311,15 +281,10 @@ internal Arm64() { } /// /// svuint32_t svand[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2) - /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// MOVPRFX Zresult, Zop1; AND Zresult.S, Pg/M, Zresult.S, Zop2.S /// svuint32_t svand[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// svuint32_t svand[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// AND Ztied2.S, Pg/M, Ztied2.S, Zop1.S /// AND Zresult.D, Zop1.D, Zop2.D - /// svuint32_t svand[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) - /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; AND Zresult.S, Pg/M, Zresult.S, Zop2.S - /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; AND Zresult.S, Pg/M, Zresult.S, Zop1.S /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -327,15 +292,10 @@ internal Arm64() { } /// /// svuint64_t svand[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2) - /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// MOVPRFX Zresult, Zop1; AND Zresult.D, Pg/M, Zresult.D, Zop2.D /// svuint64_t svand[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// svuint64_t svand[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// AND Ztied2.D, Pg/M, Ztied2.D, Zop1.D /// AND Zresult.D, Zop1.D, Zop2.D - /// svuint64_t svand[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) - /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; AND Zresult.D, Pg/M, Zresult.D, Zop2.D - /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; AND Zresult.D, Pg/M, Zresult.D, Zop1.D /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1259,15 +1219,10 @@ internal Arm64() { } /// /// svuint8_t svorr[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2) - /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// MOVPRFX Zresult, Zop1; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B /// svuint8_t svorr[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// svuint8_t svorr[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// ORR Ztied2.B, Pg/M, Ztied2.B, Zop1.B /// ORR Zresult.D, Zop1.D, Zop2.D - /// svuint8_t svorr[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) - /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B - /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; ORR Zresult.B, Pg/M, Zresult.B, Zop1.B /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1275,15 +1230,10 @@ internal Arm64() { } /// /// svint16_t svorr[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2) - /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// MOVPRFX Zresult, Zop1; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H /// svint16_t svorr[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2) + /// svint16_t svorr[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// ORR Ztied2.H, Pg/M, Ztied2.H, Zop1.H /// ORR Zresult.D, Zop1.D, Zop2.D - /// svint16_t svorr[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) - /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H - /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; ORR Zresult.H, Pg/M, Zresult.H, Zop1.H /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1291,15 +1241,10 @@ internal Arm64() { } /// /// svint32_t svorr[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2) - /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// MOVPRFX Zresult, Zop1; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S /// svint32_t svorr[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2) + /// svint32_t svorr[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// ORR Ztied2.S, Pg/M, Ztied2.S, Zop1.S /// ORR Zresult.D, Zop1.D, Zop2.D - /// svint32_t svorr[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) - /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S - /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; ORR Zresult.S, Pg/M, Zresult.S, Zop1.S /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1307,15 +1252,10 @@ internal Arm64() { } /// /// svint64_t svorr[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2) - /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// MOVPRFX Zresult, Zop1; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D /// svint64_t svorr[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2) + /// svint64_t svorr[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// ORR Ztied2.D, Pg/M, Ztied2.D, Zop1.D /// ORR Zresult.D, Zop1.D, Zop2.D - /// svint64_t svorr[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) - /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D - /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; ORR Zresult.D, Pg/M, Zresult.D, Zop1.D /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1323,15 +1263,10 @@ internal Arm64() { } /// /// svint8_t svorr[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2) - /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// MOVPRFX Zresult, Zop1; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B /// svint8_t svorr[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2) + /// svint8_t svorr[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// ORR Ztied2.B, Pg/M, Ztied2.B, Zop1.B /// ORR Zresult.D, Zop1.D, Zop2.D - /// svint8_t svorr[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) - /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B - /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; ORR Zresult.B, Pg/M, Zresult.B, Zop1.B /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1339,15 +1274,10 @@ internal Arm64() { } /// /// svuint16_t svorr[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2) - /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// MOVPRFX Zresult, Zop1; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H /// svuint16_t svorr[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// svuint16_t svorr[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// ORR Ztied2.H, Pg/M, Ztied2.H, Zop1.H /// ORR Zresult.D, Zop1.D, Zop2.D - /// svuint16_t svorr[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) - /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H - /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; ORR Zresult.H, Pg/M, Zresult.H, Zop1.H /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1355,15 +1285,10 @@ internal Arm64() { } /// /// svuint32_t svorr[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2) - /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// MOVPRFX Zresult, Zop1; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S /// svuint32_t svorr[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// svuint32_t svorr[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// ORR Ztied2.S, Pg/M, Ztied2.S, Zop1.S /// ORR Zresult.D, Zop1.D, Zop2.D - /// svuint32_t svorr[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) - /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S - /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; ORR Zresult.S, Pg/M, Zresult.S, Zop1.S /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1371,15 +1296,10 @@ internal Arm64() { } /// /// svuint64_t svorr[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2) - /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// MOVPRFX Zresult, Zop1; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D /// svuint64_t svorr[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// svuint64_t svorr[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// ORR Ztied2.D, Pg/M, Ztied2.D, Zop1.D /// ORR Zresult.D, Zop1.D, Zop2.D - /// svuint64_t svorr[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) - /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D - /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; ORR Zresult.D, Pg/M, Zresult.D, Zop1.D /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1802,15 +1722,10 @@ internal Arm64() { } /// /// svuint8_t sveor[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2) - /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// MOVPRFX Zresult, Zop1; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B /// svuint8_t sveor[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// svuint8_t sveor[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// EOR Ztied2.B, Pg/M, Ztied2.B, Zop1.B /// EOR Zresult.D, Zop1.D, Zop2.D - /// svuint8_t sveor[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) - /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B - /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; EOR Zresult.B, Pg/M, Zresult.B, Zop1.B /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1818,15 +1733,10 @@ internal Arm64() { } /// /// svint16_t sveor[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2) - /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// MOVPRFX Zresult, Zop1; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H /// svint16_t sveor[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2) + /// svint16_t sveor[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// EOR Ztied2.H, Pg/M, Ztied2.H, Zop1.H /// EOR Zresult.D, Zop1.D, Zop2.D - /// svint16_t sveor[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) - /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H - /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; EOR Zresult.H, Pg/M, Zresult.H, Zop1.H /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1834,15 +1744,10 @@ internal Arm64() { } /// /// svint32_t sveor[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2) - /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// MOVPRFX Zresult, Zop1; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S /// svint32_t sveor[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2) + /// svint32_t sveor[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// EOR Ztied2.S, Pg/M, Ztied2.S, Zop1.S /// EOR Zresult.D, Zop1.D, Zop2.D - /// svint32_t sveor[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) - /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S - /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; EOR Zresult.S, Pg/M, Zresult.S, Zop1.S /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1850,15 +1755,10 @@ internal Arm64() { } /// /// svint64_t sveor[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2) - /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// MOVPRFX Zresult, Zop1; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D /// svint64_t sveor[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2) + /// svint64_t sveor[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// EOR Ztied2.D, Pg/M, Ztied2.D, Zop1.D /// EOR Zresult.D, Zop1.D, Zop2.D - /// svint64_t sveor[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) - /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D - /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; EOR Zresult.D, Pg/M, Zresult.D, Zop1.D /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1866,15 +1766,10 @@ internal Arm64() { } /// /// svint8_t sveor[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2) - /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// MOVPRFX Zresult, Zop1; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B /// svint8_t sveor[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2) + /// svint8_t sveor[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// EOR Ztied2.B, Pg/M, Ztied2.B, Zop1.B /// EOR Zresult.D, Zop1.D, Zop2.D - /// svint8_t sveor[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) - /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B - /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; EOR Zresult.B, Pg/M, Zresult.B, Zop1.B /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1882,15 +1777,10 @@ internal Arm64() { } /// /// svuint16_t sveor[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2) - /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// MOVPRFX Zresult, Zop1; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H /// svuint16_t sveor[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// svuint16_t sveor[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// EOR Ztied2.H, Pg/M, Ztied2.H, Zop1.H /// EOR Zresult.D, Zop1.D, Zop2.D - /// svuint16_t sveor[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) - /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H - /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; EOR Zresult.H, Pg/M, Zresult.H, Zop1.H /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1898,15 +1788,10 @@ internal Arm64() { } /// /// svuint32_t sveor[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2) - /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// MOVPRFX Zresult, Zop1; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S /// svuint32_t sveor[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// svuint32_t sveor[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// EOR Ztied2.S, Pg/M, Ztied2.S, Zop1.S /// EOR Zresult.D, Zop1.D, Zop2.D - /// svuint32_t sveor[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) - /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S - /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; EOR Zresult.S, Pg/M, Zresult.S, Zop1.S /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1914,15 +1799,10 @@ internal Arm64() { } /// /// svuint64_t sveor[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2) - /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// MOVPRFX Zresult, Zop1; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D /// svuint64_t sveor[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// svuint64_t sveor[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// EOR Ztied2.D, Pg/M, Ztied2.D, Zop1.D /// EOR Zresult.D, Zop1.D, Zop2.D - /// svuint64_t sveor[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) - /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D - /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; EOR Zresult.D, Pg/M, Zresult.D, Zop1.D /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs index 29c0a836f5401..39380f8a50f9a 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs @@ -244,15 +244,10 @@ internal Arm64() { } /// /// svuint8_t svand[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2) - /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// MOVPRFX Zresult, Zop1; AND Zresult.B, Pg/M, Zresult.B, Zop2.B /// svuint8_t svand[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// svuint8_t svand[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// AND Ztied2.B, Pg/M, Ztied2.B, Zop1.B /// AND Zresult.D, Zop1.D, Zop2.D - /// svuint8_t svand[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) - /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; AND Zresult.B, Pg/M, Zresult.B, Zop2.B - /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; AND Zresult.B, Pg/M, Zresult.B, Zop1.B /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -260,15 +255,10 @@ internal Arm64() { } /// /// svint16_t svand[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2) - /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// MOVPRFX Zresult, Zop1; AND Zresult.H, Pg/M, Zresult.H, Zop2.H /// svint16_t svand[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2) + /// svint16_t svand[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// AND Ztied2.H, Pg/M, Ztied2.H, Zop1.H /// AND Zresult.D, Zop1.D, Zop2.D - /// svint16_t svand[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) - /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; AND Zresult.H, Pg/M, Zresult.H, Zop2.H - /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; AND Zresult.H, Pg/M, Zresult.H, Zop1.H /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -276,15 +266,10 @@ internal Arm64() { } /// /// svint32_t svand[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2) - /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// MOVPRFX Zresult, Zop1; AND Zresult.S, Pg/M, Zresult.S, Zop2.S /// svint32_t svand[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2) + /// svint32_t svand[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// AND Ztied2.S, Pg/M, Ztied2.S, Zop1.S /// AND Zresult.D, Zop1.D, Zop2.D - /// svint32_t svand[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) - /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; AND Zresult.S, Pg/M, Zresult.S, Zop2.S - /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; AND Zresult.S, Pg/M, Zresult.S, Zop1.S /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -292,15 +277,10 @@ internal Arm64() { } /// /// svint64_t svand[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2) - /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// MOVPRFX Zresult, Zop1; AND Zresult.D, Pg/M, Zresult.D, Zop2.D /// svint64_t svand[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2) + /// svint64_t svand[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// AND Ztied2.D, Pg/M, Ztied2.D, Zop1.D /// AND Zresult.D, Zop1.D, Zop2.D - /// svint64_t svand[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) - /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; AND Zresult.D, Pg/M, Zresult.D, Zop2.D - /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; AND Zresult.D, Pg/M, Zresult.D, Zop1.D /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -308,15 +288,10 @@ internal Arm64() { } /// /// svint8_t svand[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2) - /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// MOVPRFX Zresult, Zop1; AND Zresult.B, Pg/M, Zresult.B, Zop2.B /// svint8_t svand[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2) + /// svint8_t svand[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// AND Ztied2.B, Pg/M, Ztied2.B, Zop1.B /// AND Zresult.D, Zop1.D, Zop2.D - /// svint8_t svand[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) - /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; AND Zresult.B, Pg/M, Zresult.B, Zop2.B - /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; AND Zresult.B, Pg/M, Zresult.B, Zop1.B /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -324,15 +299,10 @@ internal Arm64() { } /// /// svuint16_t svand[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2) - /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// MOVPRFX Zresult, Zop1; AND Zresult.H, Pg/M, Zresult.H, Zop2.H /// svuint16_t svand[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// svuint16_t svand[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// AND Ztied2.H, Pg/M, Ztied2.H, Zop1.H /// AND Zresult.D, Zop1.D, Zop2.D - /// svuint16_t svand[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) - /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; AND Zresult.H, Pg/M, Zresult.H, Zop2.H - /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; AND Zresult.H, Pg/M, Zresult.H, Zop1.H /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -340,15 +310,10 @@ internal Arm64() { } /// /// svuint32_t svand[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2) - /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// MOVPRFX Zresult, Zop1; AND Zresult.S, Pg/M, Zresult.S, Zop2.S /// svuint32_t svand[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// svuint32_t svand[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// AND Ztied2.S, Pg/M, Ztied2.S, Zop1.S /// AND Zresult.D, Zop1.D, Zop2.D - /// svuint32_t svand[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) - /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; AND Zresult.S, Pg/M, Zresult.S, Zop2.S - /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; AND Zresult.S, Pg/M, Zresult.S, Zop1.S /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -356,15 +321,10 @@ internal Arm64() { } /// /// svuint64_t svand[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2) - /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// MOVPRFX Zresult, Zop1; AND Zresult.D, Pg/M, Zresult.D, Zop2.D /// svuint64_t svand[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// svuint64_t svand[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// AND Ztied2.D, Pg/M, Ztied2.D, Zop1.D /// AND Zresult.D, Zop1.D, Zop2.D - /// svuint64_t svand[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) - /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; AND Zresult.D, Pg/M, Zresult.D, Zop2.D - /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; AND Zresult.D, Pg/M, Zresult.D, Zop1.D /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1315,15 +1275,10 @@ internal Arm64() { } /// /// svuint8_t svorr[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2) - /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// MOVPRFX Zresult, Zop1; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B /// svuint8_t svorr[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// svuint8_t svorr[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// ORR Ztied2.B, Pg/M, Ztied2.B, Zop1.B /// ORR Zresult.D, Zop1.D, Zop2.D - /// svuint8_t svorr[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) - /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B - /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; ORR Zresult.B, Pg/M, Zresult.B, Zop1.B /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1331,15 +1286,10 @@ internal Arm64() { } /// /// svint16_t svorr[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2) - /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// MOVPRFX Zresult, Zop1; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H /// svint16_t svorr[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2) + /// svint16_t svorr[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// ORR Ztied2.H, Pg/M, Ztied2.H, Zop1.H /// ORR Zresult.D, Zop1.D, Zop2.D - /// svint16_t svorr[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) - /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H - /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; ORR Zresult.H, Pg/M, Zresult.H, Zop1.H /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1347,15 +1297,10 @@ internal Arm64() { } /// /// svint32_t svorr[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2) - /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// MOVPRFX Zresult, Zop1; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S /// svint32_t svorr[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2) + /// svint32_t svorr[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// ORR Ztied2.S, Pg/M, Ztied2.S, Zop1.S /// ORR Zresult.D, Zop1.D, Zop2.D - /// svint32_t svorr[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) - /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S - /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; ORR Zresult.S, Pg/M, Zresult.S, Zop1.S /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1363,15 +1308,10 @@ internal Arm64() { } /// /// svint64_t svorr[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2) - /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// MOVPRFX Zresult, Zop1; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D /// svint64_t svorr[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2) + /// svint64_t svorr[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// ORR Ztied2.D, Pg/M, Ztied2.D, Zop1.D /// ORR Zresult.D, Zop1.D, Zop2.D - /// svint64_t svorr[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) - /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D - /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; ORR Zresult.D, Pg/M, Zresult.D, Zop1.D /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1379,15 +1319,10 @@ internal Arm64() { } /// /// svint8_t svorr[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2) - /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// MOVPRFX Zresult, Zop1; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B /// svint8_t svorr[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2) + /// svint8_t svorr[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) /// ORR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// ORR Ztied2.B, Pg/M, Ztied2.B, Zop1.B /// ORR Zresult.D, Zop1.D, Zop2.D - /// svint8_t svorr[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) - /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; ORR Zresult.B, Pg/M, Zresult.B, Zop2.B - /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; ORR Zresult.B, Pg/M, Zresult.B, Zop1.B /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1395,15 +1330,10 @@ internal Arm64() { } /// /// svuint16_t svorr[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2) - /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// MOVPRFX Zresult, Zop1; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H /// svuint16_t svorr[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// svuint16_t svorr[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) /// ORR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// ORR Ztied2.H, Pg/M, Ztied2.H, Zop1.H /// ORR Zresult.D, Zop1.D, Zop2.D - /// svuint16_t svorr[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) - /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; ORR Zresult.H, Pg/M, Zresult.H, Zop2.H - /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; ORR Zresult.H, Pg/M, Zresult.H, Zop1.H /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1411,15 +1341,10 @@ internal Arm64() { } /// /// svuint32_t svorr[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2) - /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// MOVPRFX Zresult, Zop1; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S /// svuint32_t svorr[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// svuint32_t svorr[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) /// ORR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// ORR Ztied2.S, Pg/M, Ztied2.S, Zop1.S /// ORR Zresult.D, Zop1.D, Zop2.D - /// svuint32_t svorr[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) - /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; ORR Zresult.S, Pg/M, Zresult.S, Zop2.S - /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; ORR Zresult.S, Pg/M, Zresult.S, Zop1.S /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1427,15 +1352,10 @@ internal Arm64() { } /// /// svuint64_t svorr[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2) - /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// MOVPRFX Zresult, Zop1; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D /// svuint64_t svorr[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// svuint64_t svorr[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) /// ORR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// ORR Ztied2.D, Pg/M, Ztied2.D, Zop1.D /// ORR Zresult.D, Zop1.D, Zop2.D - /// svuint64_t svorr[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) - /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; ORR Zresult.D, Pg/M, Zresult.D, Zop2.D - /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; ORR Zresult.D, Pg/M, Zresult.D, Zop1.D /// svbool_t svorr[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// ORR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1884,15 +1804,10 @@ internal Arm64() { } /// /// svuint8_t sveor[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2) - /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// MOVPRFX Zresult, Zop1; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B /// svuint8_t sveor[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2) + /// svuint8_t sveor[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// EOR Ztied2.B, Pg/M, Ztied2.B, Zop1.B /// EOR Zresult.D, Zop1.D, Zop2.D - /// svuint8_t sveor[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2) - /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B - /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; EOR Zresult.B, Pg/M, Zresult.B, Zop1.B /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1900,15 +1815,10 @@ internal Arm64() { } /// /// svint16_t sveor[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2) - /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// MOVPRFX Zresult, Zop1; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H /// svint16_t sveor[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2) + /// svint16_t sveor[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// EOR Ztied2.H, Pg/M, Ztied2.H, Zop1.H /// EOR Zresult.D, Zop1.D, Zop2.D - /// svint16_t sveor[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2) - /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H - /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; EOR Zresult.H, Pg/M, Zresult.H, Zop1.H /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1916,15 +1826,10 @@ internal Arm64() { } /// /// svint32_t sveor[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2) - /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// MOVPRFX Zresult, Zop1; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S /// svint32_t sveor[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2) + /// svint32_t sveor[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// EOR Ztied2.S, Pg/M, Ztied2.S, Zop1.S /// EOR Zresult.D, Zop1.D, Zop2.D - /// svint32_t sveor[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2) - /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S - /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; EOR Zresult.S, Pg/M, Zresult.S, Zop1.S /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1932,15 +1837,10 @@ internal Arm64() { } /// /// svint64_t sveor[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2) - /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// MOVPRFX Zresult, Zop1; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D /// svint64_t sveor[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2) + /// svint64_t sveor[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// EOR Ztied2.D, Pg/M, Ztied2.D, Zop1.D /// EOR Zresult.D, Zop1.D, Zop2.D - /// svint64_t sveor[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2) - /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D - /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; EOR Zresult.D, Pg/M, Zresult.D, Zop1.D /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1948,15 +1848,10 @@ internal Arm64() { } /// /// svint8_t sveor[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2) - /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// MOVPRFX Zresult, Zop1; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B /// svint8_t sveor[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2) + /// svint8_t sveor[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) /// EOR Ztied1.B, Pg/M, Ztied1.B, Zop2.B - /// EOR Ztied2.B, Pg/M, Ztied2.B, Zop1.B /// EOR Zresult.D, Zop1.D, Zop2.D - /// svint8_t sveor[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2) - /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; EOR Zresult.B, Pg/M, Zresult.B, Zop2.B - /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; EOR Zresult.B, Pg/M, Zresult.B, Zop1.B /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1964,15 +1859,10 @@ internal Arm64() { } /// /// svuint16_t sveor[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2) - /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// MOVPRFX Zresult, Zop1; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H /// svuint16_t sveor[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2) + /// svuint16_t sveor[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) /// EOR Ztied1.H, Pg/M, Ztied1.H, Zop2.H - /// EOR Ztied2.H, Pg/M, Ztied2.H, Zop1.H /// EOR Zresult.D, Zop1.D, Zop2.D - /// svuint16_t sveor[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2) - /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; EOR Zresult.H, Pg/M, Zresult.H, Zop2.H - /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; EOR Zresult.H, Pg/M, Zresult.H, Zop1.H /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1980,15 +1870,10 @@ internal Arm64() { } /// /// svuint32_t sveor[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2) - /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// MOVPRFX Zresult, Zop1; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S /// svuint32_t sveor[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2) + /// svuint32_t sveor[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) /// EOR Ztied1.S, Pg/M, Ztied1.S, Zop2.S - /// EOR Ztied2.S, Pg/M, Ztied2.S, Zop1.S /// EOR Zresult.D, Zop1.D, Zop2.D - /// svuint32_t sveor[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2) - /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; EOR Zresult.S, Pg/M, Zresult.S, Zop2.S - /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; EOR Zresult.S, Pg/M, Zresult.S, Zop1.S /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B /// @@ -1996,15 +1881,10 @@ internal Arm64() { } /// /// svuint64_t sveor[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2) - /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// MOVPRFX Zresult, Zop1; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D /// svuint64_t sveor[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2) + /// svuint64_t sveor[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) /// EOR Ztied1.D, Pg/M, Ztied1.D, Zop2.D - /// EOR Ztied2.D, Pg/M, Ztied2.D, Zop1.D /// EOR Zresult.D, Zop1.D, Zop2.D - /// svuint64_t sveor[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2) - /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; EOR Zresult.D, Pg/M, Zresult.D, Zop2.D - /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; EOR Zresult.D, Pg/M, Zresult.D, Zop1.D /// svbool_t sveor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) /// EOR Presult.B, Pg/Z, Pop1.B, Pop2.B ///