From 90cb0d01bfba2af5c0504832d93da732c58350e9 Mon Sep 17 00:00:00 2001 From: EgorBo Date: Wed, 15 Jun 2022 21:26:17 +0200 Subject: [PATCH 1/3] Don't use addressing modes for volatile loads for gc types --- src/coreclr/jit/lower.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/coreclr/jit/lower.cpp b/src/coreclr/jit/lower.cpp index fb8e0104d34d7..a2e195ad3ae52 100644 --- a/src/coreclr/jit/lower.cpp +++ b/src/coreclr/jit/lower.cpp @@ -5215,7 +5215,7 @@ bool Lowering::TryCreateAddrMode(GenTree* addr, bool isContainable, GenTree* par } #ifdef TARGET_ARM64 - if (parent->OperIsIndir() && parent->AsIndir()->IsVolatile() && !varTypeIsGC(addr)) + if (parent->OperIsIndir() && parent->AsIndir()->IsVolatile()) { // For Arm64 we avoid using LEA for volatile INDs // because we won't be able to use ldar/star From 08a61dbfdaa75a7941a939eb7a338cf0c31dca43 Mon Sep 17 00:00:00 2001 From: EgorBo Date: Fri, 17 Jun 2022 00:54:42 +0200 Subject: [PATCH 2/3] print perfscore --- src/coreclr/scripts/superpmi_diffs.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/coreclr/scripts/superpmi_diffs.py b/src/coreclr/scripts/superpmi_diffs.py index 47243ad43d3a2..33050897d0b2e 100644 --- a/src/coreclr/scripts/superpmi_diffs.py +++ b/src/coreclr/scripts/superpmi_diffs.py @@ -207,6 +207,8 @@ def main(main_args): os.path.join(script_dir, "superpmi.py"), "asmdiffs", "--no_progress", + "-metrics", "CodeSize", + "-metrics", "PerfScore", "-core_root", core_root_dir, "-target_os", platform_name, "-target_arch", arch_name, From 1f76c43db0cc80909869c144affed7d0a14b153c Mon Sep 17 00:00:00 2001 From: EgorBo Date: Fri, 17 Jun 2022 01:48:59 +0200 Subject: [PATCH 3/3] fix assert --- src/coreclr/jit/gcinfo.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/coreclr/jit/gcinfo.cpp b/src/coreclr/jit/gcinfo.cpp index 1d0229fbf26f5..be152e4b38b10 100644 --- a/src/coreclr/jit/gcinfo.cpp +++ b/src/coreclr/jit/gcinfo.cpp @@ -302,9 +302,10 @@ GCInfo::WriteBarrierForm GCInfo::gcWriteBarrierFormFromTargetAddress(GenTree* tg GenTree* addOp2 = tgtAddr->AsOp()->gtGetOp2(); var_types addOp1Type = addOp1->TypeGet(); var_types addOp2Type = addOp2->TypeGet(); + if (addOp1Type == TYP_BYREF || addOp1Type == TYP_REF) { - assert(addOp2Type != TYP_BYREF && addOp2Type != TYP_REF); + assert(((addOp2Type != TYP_BYREF) || (addOp2->OperIs(GT_CNS_INT))) && (addOp2Type != TYP_REF)); tgtAddr = addOp1; simplifiedExpr = true; }