diff --git a/src/coreclr/jit/hwintrinsiclistarm64sve.h b/src/coreclr/jit/hwintrinsiclistarm64sve.h
new file mode 100644
index 0000000000000..c23aa1aa14ca4
--- /dev/null
+++ b/src/coreclr/jit/hwintrinsiclistarm64sve.h
@@ -0,0 +1,684 @@
+// Licensed to the .NET Foundation under one or more agreements.
+// The .NET Foundation licenses this file to you under the MIT license.
+
+/*****************************************************************************/
+#ifndef HARDWARE_INTRINSIC
+#error Define HARDWARE_INTRINSIC before including this file
+#endif
+/*****************************************************************************/
+
+// clang-format off
+
+#ifdef FEATURE_HW_INTRINSICS
+
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags
+// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// Sve
+HARDWARE_INTRINSIC(Sve, Abs, -1, 1, true, {INS_SVE_ABS, INS_invalid, INS_SVE_ABS, INS_invalid, INS_SVE_ABS, INS_invalid, INS_SVE_ABS, INS_invalid, INS_SVE_FABS, INS_SVE_FABS} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, AbsoluteCompareGreaterThan, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FACGT, INS_SVE_FACGT} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, AbsoluteCompareGreaterThanOrEqual, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FACGE, INS_SVE_FACGE} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, AbsoluteCompareLessThan, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FACGT, INS_SVE_FACGT} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, AbsoluteCompareLessThanOrEqual, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FACGE, INS_SVE_FACGE} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, AbsoluteDifference, -1, 2, true, {INS_SVE_SABD, INS_SVE_UABD, INS_SVE_SABD, INS_SVE_UABD, INS_SVE_SABD, INS_SVE_UABD, INS_SVE_SABD, INS_SVE_UABD, INS_SVE_FABD, INS_SVE_FABD} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Add, -1, 2, true, {INS_SVE_ADD, INS_SVE_ADD, INS_SVE_ADD, INS_SVE_ADD, INS_SVE_ADD, INS_SVE_ADD, INS_SVE_ADD, INS_SVE_ADD, INS_SVE_FADD, INS_SVE_FADD} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, AddAcross, -1, 1, true, {INS_SVE_SADDV, INS_SVE_UADDV, INS_SVE_SADDV, INS_SVE_UADDV, INS_SVE_SADDV, INS_SVE_UADDV, INS_SVE_UADDV, INS_SVE_UADDV, INS_SVE_FADDV, INS_SVE_FADDV} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, AddRotateComplex, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCADD, INS_SVE_FCADD} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, AddSaturate, -1, 2, true, {INS_SVE_SQADD, INS_SVE_UQADD, INS_SVE_SQADD, INS_SVE_UQADD, INS_SVE_SQADD, INS_SVE_UQADD, INS_SVE_SQADD, INS_SVE_UQADD, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, AddSequentialAcross, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FADDA, INS_SVE_FADDA} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, And, -1, 2, true, {INS_SVE_AND, INS_SVE_AND, INS_SVE_AND, INS_SVE_AND, INS_SVE_AND, INS_SVE_AND, INS_SVE_AND, INS_SVE_AND, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, AndAcross, -1, 1, true, {INS_SVE_ANDV, INS_SVE_ANDV, INS_SVE_ANDV, INS_SVE_ANDV, INS_SVE_ANDV, INS_SVE_ANDV, INS_SVE_ANDV, INS_SVE_ANDV, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, AndNot, -1, 2, true, {INS_SVE_NAND, INS_SVE_NAND, INS_SVE_NAND, INS_SVE_NAND, INS_SVE_NAND, INS_SVE_NAND, INS_SVE_NAND, INS_SVE_NAND, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, BitwiseClear, -1, 2, true, {INS_SVE_BIC, INS_SVE_BIC, INS_SVE_BIC, INS_SVE_BIC, INS_SVE_BIC, INS_SVE_BIC, INS_SVE_BIC, INS_SVE_BIC, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Cnot, -1, 1, true, {INS_SVE_CNOT, INS_SVE_CNOT, INS_SVE_CNOT, INS_SVE_CNOT, INS_SVE_CNOT, INS_SVE_CNOT, INS_SVE_CNOT, INS_SVE_CNOT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Compact, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_COMPACT, INS_SVE_COMPACT, INS_SVE_COMPACT, INS_SVE_COMPACT, INS_SVE_COMPACT, INS_SVE_COMPACT} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, CompareEqual, -1, 2, true, {INS_SVE_CMPEQ, INS_SVE_CMPEQ, INS_SVE_CMPEQ, INS_SVE_CMPEQ, INS_SVE_CMPEQ, INS_SVE_CMPEQ, INS_SVE_CMPEQ, INS_SVE_CMPEQ, INS_SVE_FCMEQ, INS_SVE_FCMEQ} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, CompareGreaterThan, -1, 2, true, {INS_SVE_CMPGT, INS_SVE_CMPHI, INS_SVE_CMPGT, INS_SVE_CMPHI, INS_SVE_CMPGT, INS_SVE_CMPHI, INS_SVE_CMPGT, INS_SVE_CMPHI, INS_SVE_FCMGT, INS_SVE_FCMGT} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, CompareGreaterThanOrEqual, -1, 2, true, {INS_SVE_CMPGE, INS_SVE_CMPHS, INS_SVE_CMPGE, INS_SVE_CMPHS, INS_SVE_CMPGE, INS_SVE_CMPHS, INS_SVE_CMPGE, INS_SVE_CMPHS, INS_SVE_FCMGE, INS_SVE_FCMGE} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, CompareLessThan, -1, 2, true, {INS_SVE_CMPGT/INS_SVE_CMPLT,INS_SVE_CMPHI/INS_SVE_CMPLO,INS_SVE_CMPGT/INS_SVE_CMPLT,INS_SVE_CMPHI/INS_SVE_CMPLO,INS_SVE_CMPGT/INS_SVE_CMPLT,INS_SVE_CMPHI/INS_SVE_CMPLO,INS_SVE_CMPGT, INS_SVE_CMPHI, INS_SVE_FCMGT, INS_SVE_FCMGT} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, CompareLessThanOrEqual, -1, 2, true, {INS_SVE_CMPGE/INS_SVE_CMPLE,INS_SVE_CMPHS/INS_SVE_CMPLS,INS_SVE_CMPGE/INS_SVE_CMPLE,INS_SVE_CMPHS/INS_SVE_CMPLS,INS_SVE_CMPGE/INS_SVE_CMPLE,INS_SVE_CMPHS/INS_SVE_CMPLS,INS_SVE_CMPGE, INS_SVE_CMPHS, INS_SVE_FCMGE, INS_SVE_FCMGE} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, CompareNotEqualTo, -1, 2, true, {INS_SVE_CMPNE, INS_SVE_CMPNE, INS_SVE_CMPNE, INS_SVE_CMPNE, INS_SVE_CMPNE, INS_SVE_CMPNE, INS_SVE_CMPNE, INS_SVE_CMPNE, INS_SVE_FCMNE, INS_SVE_FCMNE} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, CompareUnordered, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCMUO, INS_SVE_FCMUO} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ComputeByteAddresses, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ADR, INS_invalid, INS_SVE_ADR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ComputeInt16Addresses, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ADR, INS_invalid, INS_SVE_ADR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ComputeInt32Addresses, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ADR, INS_invalid, INS_SVE_ADR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ComputeInt64Addresses, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ADR, INS_invalid, INS_SVE_ADR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ConditionalExtractAfterLastActiveElement, -1, 3, true, {INS_SVE_CLASTA, INS_SVE_CLASTA, INS_SVE_CLASTA, INS_SVE_CLASTA, INS_SVE_CLASTA, INS_SVE_CLASTA, INS_SVE_CLASTA, INS_SVE_CLASTA, INS_SVE_CLASTA, INS_SVE_CLASTA} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ConditionalExtractLastActiveElement, -1, 3, true, {INS_SVE_CLASTB, INS_SVE_CLASTB, INS_SVE_CLASTB, INS_SVE_CLASTB, INS_SVE_CLASTB, INS_SVE_CLASTB, INS_SVE_CLASTB, INS_SVE_CLASTB, INS_SVE_CLASTB, INS_SVE_CLASTB} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ConditionalSelect, -1, 3, true, {INS_SVE_SEL, INS_SVE_SEL, INS_SVE_SEL, INS_SVE_SEL, INS_SVE_SEL, INS_SVE_SEL, INS_SVE_SEL, INS_SVE_SEL, INS_SVE_SEL, INS_SVE_SEL} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ConvertToDouble, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVT/INS_SVE_SCVTF/INS_SVE_UCVTF}HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ConvertToInt32, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTZS, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ConvertToInt64, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTZS, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ConvertToSingle, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVT/INS_SVE_SCVTF/INS_SVE_UCVTF,INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ConvertToUInt32, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTZU, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ConvertToUInt64, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTZU, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, Count16BitElements, -1, 0, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Count32BitElements, -1, 0, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Count64BitElements, -1, 0, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Count8BitElements, -1, 0, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, CreateBreakAfterMask, -1, 2, true, {INS_SVE_BRKA, INS_SVE_BRKA, INS_SVE_BRKA, INS_SVE_BRKA, INS_SVE_BRKA, INS_SVE_BRKA, INS_SVE_BRKA, INS_SVE_BRKA, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, CreateBreakAfterPropagateMask, -1, 3, true, {INS_SVE_BRKPA, INS_SVE_BRKPA, INS_SVE_BRKPA, INS_SVE_BRKPA, INS_SVE_BRKPA, INS_SVE_BRKPA, INS_SVE_BRKPA, INS_SVE_BRKPA, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, CreateBreakBeforeMask, -1, 2, true, {INS_SVE_BRKB, INS_SVE_BRKB, INS_SVE_BRKB, INS_SVE_BRKB, INS_SVE_BRKB, INS_SVE_BRKB, INS_SVE_BRKB, INS_SVE_BRKB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, CreateBreakBeforePropagateMask, -1, 3, true, {INS_SVE_BRKPB, INS_SVE_BRKPB, INS_SVE_BRKPB, INS_SVE_BRKPB, INS_SVE_BRKPB, INS_SVE_BRKPB, INS_SVE_BRKPB, INS_SVE_BRKPB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, CreateSeries, -1, 2, true, {INS_SVE_INDEX, INS_SVE_INDEX, INS_SVE_INDEX, INS_SVE_INDEX, INS_SVE_INDEX, INS_SVE_INDEX, INS_SVE_INDEX, INS_SVE_INDEX, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, CreateWhileLessThanMask, -1, 2, true, {INS_invalid, INS_SVE_WHILELT/INS_SVE_WHILELO,INS_invalid, INS_SVE_WHILELT/INS_SVE_WHILELO,INS_invalid, INS_SVE_WHILELT/INS_SVE_WHILELO,INS_invalid, INS_SVE_WHILELT/INS_SVE_WHILELO,INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, CreateWhileLessThanOrEqualMask, -1, 2, true, {INS_invalid, INS_SVE_WHILELE/INS_SVE_WHILELS,INS_invalid, INS_SVE_WHILELE/INS_SVE_WHILELS,INS_invalid, INS_SVE_WHILELE/INS_SVE_WHILELS,INS_invalid, INS_SVE_WHILELE/INS_SVE_WHILELS,INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, Divide, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SDIV, INS_SVE_UDIV, INS_SVE_SDIV, INS_SVE_UDIV, INS_SVE_FDIV, INS_SVE_FDIV} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, DotProduct, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SDOT, INS_SVE_UDOT, INS_SVE_SDOT, INS_SVE_UDOT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, DuplicateSelectedScalarToVector, -1, 1, true, {INS_SVE_DUP/INS_SVE_FDUP/INS_SVE_DUPM/INS_SVE_TBL,INS_SVE_DUP/INS_SVE_FDUP/INS_SVE_DUPM/INS_SVE_TBL,INS_SVE_DUP/INS_SVE_FDUP/INS_SVE_DUPM/INS_SVE_TBL,INS_SVE_DUP/INS_SVE_FDUP/INS_SVE_DUPM/INS_SVE_TBL,INS_SVE_DUP/INS_SVE_FDUP/INS_SVE_DUPM/INS_SVE_TBL,INS_SVE_DUP/INS_SVE_FDUP/INS_SVE_DUPM/INS_SVE_TBL,INS_SVE_DUP/INS_SVE_FDUP/INS_SVE_DUPM/INS_SVE_TBL,INS_SVE_DUP/INS_SVE_FDUP/INS_SVE_DUPM/INS_SVE_TBL,INS_SVE_DUP/INS_SVE_FDUP/INS_SVE_TBL,INS_SVE_DUP/INS_SVE_FDUP/INS_SVE_TBL}HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ExtractAfterLast, -1, 1, true, {INS_SVE_LASTA, INS_SVE_LASTA, INS_SVE_LASTA, INS_SVE_LASTA, INS_SVE_LASTA, INS_SVE_LASTA, INS_SVE_LASTA, INS_SVE_LASTA, INS_SVE_LASTA, INS_SVE_LASTA} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ExtractLast, -1, 1, true, {INS_SVE_LASTB, INS_SVE_LASTB, INS_SVE_LASTB, INS_SVE_LASTB, INS_SVE_LASTB, INS_SVE_LASTB, INS_SVE_LASTB, INS_SVE_LASTB, INS_SVE_LASTB, INS_SVE_LASTB} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ExtractVector, -1, 3, true, {INS_SVE_EXT, INS_SVE_EXT, INS_SVE_EXT, INS_SVE_EXT, INS_SVE_EXT, INS_SVE_EXT, INS_SVE_EXT, INS_SVE_EXT, INS_SVE_EXT, INS_SVE_EXT} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, FalseMask, -1, 0, false, {INS_invalid, INS_SVE_PFALSE, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, FloatingPointExponentialAccelerator, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FEXPA, INS_SVE_FEXPA} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve, FusedMultiplyAdd, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMLA, INS_SVE_FMLA} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, FusedMultiplyAddNegate, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FNMLA, INS_SVE_FNMLA} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, FusedMultiplySubtract, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMLS, INS_SVE_FMLS} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, FusedMultiplySubtractNegate, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FNMLS, INS_SVE_FNMLS} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, GatherPrefetchBytes, -1, 3, false, {INS_invalid, INS_SVE_PRFB, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherPrefetchInt16, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_PRFH/INS_SVE_PRFB,INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherPrefetchInt32, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_PRFW/INS_SVE_PRFB,INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherPrefetchInt64, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_PRFD/INS_SVE_PRFB,INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVector, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1W, INS_SVE_LD1W, INS_SVE_LD1D, INS_SVE_LD1D, INS_SVE_LD1W, INS_SVE_LD1D} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorByteSignExtend, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SB, INS_SVE_LD1SB, INS_SVE_LD1SB, INS_SVE_LD1SB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorByteSignExtendFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDFF1SB, INS_SVE_LDFF1SB, INS_SVE_LDFF1SB, INS_SVE_LDFF1SB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorByteZeroExtend, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1B, INS_SVE_LD1B, INS_SVE_LD1B, INS_SVE_LD1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorByteZeroExtendFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDFF1B, INS_SVE_LDFF1B, INS_SVE_LDFF1B, INS_SVE_LDFF1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDFF1W, INS_SVE_LDFF1W, INS_SVE_LDFF1D, INS_SVE_LDFF1D, INS_SVE_LDFF1W, INS_SVE_LDFF1D} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorInt16SignExtend, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SH, INS_SVE_LD1SH, INS_SVE_LD1SH, INS_SVE_LD1SH, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorInt16SignExtendFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDFF1SH, INS_SVE_LDFF1SH, INS_SVE_LDFF1SH, INS_SVE_LDFF1SH, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorInt16ZeroExtend, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1H, INS_SVE_LD1H, INS_SVE_LD1H, INS_SVE_LD1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorInt16ZeroExtendFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDFF1H, INS_SVE_LDFF1H, INS_SVE_LDFF1H, INS_SVE_LDFF1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorInt32SignExtend, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SW, INS_SVE_LD1SW, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorInt32SignExtendFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDFF1SW, INS_SVE_LDFF1SW, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorInt32ZeroExtend, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1W, INS_SVE_LD1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GatherVectorInt32ZeroExtendFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDFF1W, INS_SVE_LDFF1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, GetActiveElementCount, -1, 2, true, {INS_invalid, INS_SVE_CNTP, INS_invalid, INS_SVE_CNTP, INS_invalid, INS_SVE_CNTP, INS_invalid, INS_SVE_CNTP, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, GetFFR, -1, 0, true, {INS_SVE_RDFFR, INS_SVE_RDFFR, INS_SVE_RDFFR, INS_SVE_RDFFR, INS_SVE_RDFFR, INS_SVE_RDFFR, INS_SVE_RDFFR, INS_SVE_RDFFR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, InsertIntoShiftedVector, -1, 2, true, {INS_SVE_INSR, INS_SVE_INSR, INS_SVE_INSR, INS_SVE_INSR, INS_SVE_INSR, INS_SVE_INSR, INS_SVE_INSR, INS_SVE_INSR, INS_SVE_INSR, INS_SVE_INSR} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LeadingSignCount, -1, 1, true, {INS_invalid, INS_SVE_CLS, INS_invalid, INS_SVE_CLS, INS_invalid, INS_SVE_CLS, INS_invalid, INS_SVE_CLS, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve, LeadingZeroCount, -1, 1, true, {INS_invalid, INS_SVE_CLZ, INS_invalid, INS_SVE_CLZ, INS_invalid, INS_SVE_CLZ, INS_invalid, INS_SVE_CLZ, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, LoadVector, -1, 2, true, {INS_SVE_LD1B, INS_SVE_LD1B, INS_SVE_LD1H, INS_SVE_LD1H, INS_SVE_LD1W, INS_SVE_LD1W, INS_SVE_LD1D, INS_SVE_LD1D, INS_SVE_LD1W, INS_SVE_LD1D} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVector128AndReplicateToVector, -1, 2, true, {INS_SVE_LD1RQB, INS_SVE_LD1RQB, INS_SVE_LD1RQH, INS_SVE_LD1RQH, INS_SVE_LD1RQW, INS_SVE_LD1RQW, INS_SVE_LD1RQD, INS_SVE_LD1RQD, INS_SVE_LD1RQW, INS_SVE_LD1RQD} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_LDFF1SB, INS_SVE_LDFF1SB, INS_SVE_LDFF1SB, INS_SVE_LDFF1SB, INS_SVE_LDFF1SB, INS_SVE_LDFF1SB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendNonFaultingToInt16, -1, 2, false, {INS_invalid, INS_invalid, INS_SVE_LDNF1SB, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendNonFaultingToInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1SB, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendNonFaultingToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1SB, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendNonFaultingToUInt16, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1SB, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendNonFaultingToUInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1SB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendNonFaultingToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1SB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendToInt16, -1, 2, false, {INS_invalid, INS_invalid, INS_SVE_LD1SB, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendToInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SB, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SB, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendToUInt16, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SB, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendToUInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteSignExtendToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_LDFF1B, INS_SVE_LDFF1B, INS_SVE_LDFF1B, INS_SVE_LDFF1B, INS_SVE_LDFF1B, INS_SVE_LDFF1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendNonFaultingToInt16, -1, 2, false, {INS_invalid, INS_invalid, INS_SVE_LDNF1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendNonFaultingToInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendNonFaultingToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1B, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendNonFaultingToUInt16, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendNonFaultingToUInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendNonFaultingToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendToInt16, -1, 2, false, {INS_invalid, INS_invalid, INS_SVE_LD1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendToInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1B, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendToUInt16, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendToUInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorByteZeroExtendToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorFirstFaulting, -1, 2, true, {INS_SVE_LDFF1B, INS_SVE_LDFF1B, INS_SVE_LDFF1H, INS_SVE_LDFF1H, INS_SVE_LDFF1W, INS_SVE_LDFF1W, INS_SVE_LDFF1D, INS_SVE_LDFF1D, INS_SVE_LDFF1W, INS_SVE_LDFF1D} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16SignExtendFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDFF1SH, INS_SVE_LDFF1SH, INS_SVE_LDFF1SH, INS_SVE_LDFF1SH, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16SignExtendNonFaultingToInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1SH, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16SignExtendNonFaultingToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1SH, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16SignExtendNonFaultingToUInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1SH, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16SignExtendNonFaultingToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1SH, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16SignExtendToInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SH, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16SignExtendToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SH, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16SignExtendToUInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SH, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16SignExtendToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SH, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16ZeroExtendFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDFF1H, INS_SVE_LDFF1H, INS_SVE_LDFF1H, INS_SVE_LDFF1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16ZeroExtendNonFaultingToInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1H, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16ZeroExtendNonFaultingToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1H, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16ZeroExtendNonFaultingToUInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1H, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16ZeroExtendNonFaultingToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16ZeroExtendToInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1H, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16ZeroExtendToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1H, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16ZeroExtendToUInt32, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1H, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt16ZeroExtendToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt32SignExtendFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDFF1SW, INS_SVE_LDFF1SW, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt32SignExtendNonFaultingToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1SW, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt32SignExtendNonFaultingToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1SW, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt32SignExtendToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SW, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt32SignExtendToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1SW, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt32ZeroExtendFirstFaulting, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDFF1W, INS_SVE_LDFF1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt32ZeroExtendNonFaultingToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1W, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt32ZeroExtendNonFaultingToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNF1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt32ZeroExtendToInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1W, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorInt32ZeroExtendToUInt64, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LD1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorNonFaulting, -1, 2, true, {INS_SVE_LDNF1B, INS_SVE_LDNF1B, INS_SVE_LDNF1H, INS_SVE_LDNF1H, INS_SVE_LDNF1W, INS_SVE_LDNF1W, INS_SVE_LDNF1D, INS_SVE_LDNF1D, INS_SVE_LDNF1W, INS_SVE_LDNF1D} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorNonTemporal, -1, 2, true, {INS_SVE_LDNT1B, INS_SVE_LDNT1B, INS_SVE_LDNT1H, INS_SVE_LDNT1H, INS_SVE_LDNT1W, INS_SVE_LDNT1W, INS_SVE_LDNT1D, INS_SVE_LDNT1D, INS_SVE_LDNT1W, INS_SVE_LDNT1D} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, LoadVectorx2, -1, 2, true, {INS_SVE_LD2B, INS_SVE_LD2B, INS_SVE_LD2H, INS_SVE_LD2H, INS_SVE_LD2W, INS_SVE_LD2W, INS_SVE_LD2D, INS_SVE_LD2D, INS_SVE_LD2W, INS_SVE_LD2D} HW_Category_SIMD, HW_Flag_MultiReg)
+HARDWARE_INTRINSIC(Sve, LoadVectorx3, -1, 2, true, {INS_SVE_LD3B, INS_SVE_LD3B, INS_SVE_LD3H, INS_SVE_LD3H, INS_SVE_LD3W, INS_SVE_LD3W, INS_SVE_LD3D, INS_SVE_LD3D, INS_SVE_LD3W, INS_SVE_LD3D} HW_Category_SIMD, HW_Flag_MultiReg)
+HARDWARE_INTRINSIC(Sve, LoadVectorx4, -1, 2, true, {INS_SVE_LD4B, INS_SVE_LD4B, INS_SVE_LD4H, INS_SVE_LD4H, INS_SVE_LD4W, INS_SVE_LD4W, INS_SVE_LD4D, INS_SVE_LD4D, INS_SVE_LD4W, INS_SVE_LD4D} HW_Category_SIMD, HW_Flag_MultiReg)
+HARDWARE_INTRINSIC(Sve, MaskGetFirstSet, -1, 2, true, {INS_invalid, INS_SVE_PNEXT, INS_invalid, INS_SVE_PNEXT, INS_invalid, INS_SVE_PNEXT, INS_invalid, INS_SVE_PNEXT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MaskSetFirst, -1, 2, true, {INS_SVE_PFIRST, INS_SVE_PFIRST, INS_SVE_PFIRST, INS_SVE_PFIRST, INS_SVE_PFIRST, INS_SVE_PFIRST, INS_SVE_PFIRST, INS_SVE_PFIRST, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MaskTestAnyTrue, -1, 2, true, {INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MaskTestFirstTrue, -1, 2, true, {INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MaskTestLastTrue, -1, 2, true, {INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_SVE_PTEST, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Max, -1, 2, true, {INS_SVE_SMAX, INS_SVE_UMAX, INS_SVE_SMAX, INS_SVE_UMAX, INS_SVE_SMAX, INS_SVE_UMAX, INS_SVE_SMAX, INS_SVE_UMAX, INS_SVE_FMAX, INS_SVE_FMAX} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MaxAcross, -1, 1, true, {INS_SVE_SMAXV, INS_SVE_UMAXV, INS_SVE_SMAXV, INS_SVE_UMAXV, INS_SVE_SMAXV, INS_SVE_UMAXV, INS_SVE_SMAXV, INS_SVE_UMAXV, INS_SVE_FMAXV, INS_SVE_FMAXV} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MaxNumber, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMAXNM, INS_SVE_FMAXNM} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MaxNumberAcross, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMAXNMV, INS_SVE_FMAXNMV} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Min, -1, 2, true, {INS_SVE_SMIN, INS_SVE_UMIN, INS_SVE_SMIN, INS_SVE_UMIN, INS_SVE_SMIN, INS_SVE_UMIN, INS_SVE_SMIN, INS_SVE_UMIN, INS_SVE_FMIN, INS_SVE_FMIN} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MinAcross, -1, 1, true, {INS_SVE_SMINV, INS_SVE_UMINV, INS_SVE_SMINV, INS_SVE_UMINV, INS_SVE_SMINV, INS_SVE_UMINV, INS_SVE_SMINV, INS_SVE_UMINV, INS_SVE_FMINV, INS_SVE_FMINV} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MinNumber, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMINNM, INS_SVE_FMINNM} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MinNumberAcross, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMINNMV, INS_SVE_FMINNMV} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Multiply, -1, 2, true, {INS_SVE_MUL, INS_SVE_MUL, INS_SVE_MUL, INS_SVE_MUL, INS_SVE_MUL, INS_SVE_MUL, INS_SVE_MUL, INS_SVE_MUL, INS_SVE_FMUL, INS_SVE_FMUL} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, MultiplyAdd, -1, 3, true, {INS_SVE_MLA, INS_SVE_MLA, INS_SVE_MLA, INS_SVE_MLA, INS_SVE_MLA, INS_SVE_MLA, INS_SVE_MLA, INS_SVE_MLA, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MultiplyAddRotateComplex, -1, 4, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCMLA, INS_SVE_FCMLA} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, MultiplyExtended, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMULX, INS_SVE_FMULX} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MultiplyReturningHighHalf, -1, 2, true, {INS_SVE_SMULH, INS_SVE_UMULH, INS_SVE_SMULH, INS_SVE_UMULH, INS_SVE_SMULH, INS_SVE_UMULH, INS_SVE_SMULH, INS_SVE_UMULH, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, MultiplySubtract, -1, 3, true, {INS_SVE_MLS, INS_SVE_MLS, INS_SVE_MLS, INS_SVE_MLS, INS_SVE_MLS, INS_SVE_MLS, INS_SVE_MLS, INS_SVE_MLS, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Negate, -1, 1, true, {INS_SVE_NEG, INS_invalid, INS_SVE_NEG, INS_invalid, INS_SVE_NEG, INS_invalid, INS_SVE_NEG, INS_invalid, INS_SVE_FNEG, INS_SVE_FNEG} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Not, -1, 1, true, {INS_SVE_NOT, INS_SVE_NOT, INS_SVE_NOT, INS_SVE_NOT, INS_SVE_NOT, INS_SVE_NOT, INS_SVE_NOT, INS_SVE_NOT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Or, -1, 2, true, {INS_SVE_ORR, INS_SVE_ORR, INS_SVE_ORR, INS_SVE_ORR, INS_SVE_ORR, INS_SVE_ORR, INS_SVE_ORR, INS_SVE_ORR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, OrAcross, -1, 1, true, {INS_SVE_ORV, INS_SVE_ORV, INS_SVE_ORV, INS_SVE_ORV, INS_SVE_ORV, INS_SVE_ORV, INS_SVE_ORV, INS_SVE_ORV, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, OrNot, -1, 2, true, {INS_SVE_NOR, INS_SVE_NOR, INS_SVE_NOR, INS_SVE_NOR, INS_SVE_NOR, INS_SVE_NOR, INS_SVE_NOR, INS_SVE_NOR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, PopCount, -1, 1, true, {INS_invalid, INS_SVE_CNT, INS_invalid, INS_SVE_CNT, INS_invalid, INS_SVE_CNT, INS_invalid, INS_SVE_CNT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, PrefetchBytes, -1, 3, false, {INS_invalid, INS_SVE_PRFB, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, PrefetchInt16, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_PRFH, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, PrefetchInt32, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_PRFW, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, PrefetchInt64, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_PRFD, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, PropagateBreak, -1, 2, true, {INS_SVE_BRKN, INS_SVE_BRKN, INS_SVE_BRKN, INS_SVE_BRKN, INS_SVE_BRKN, INS_SVE_BRKN, INS_SVE_BRKN, INS_SVE_BRKN, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ReciprocalEstimate, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FRECPE, INS_SVE_FRECPE} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ReciprocalExponent, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FRECPX, INS_SVE_FRECPX} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ReciprocalSqrtEstimate, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FRSQRTE, INS_SVE_FRSQRTE} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ReciprocalSqrtStep, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FRSQRTS, INS_SVE_FRSQRTS} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ReciprocalStep, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FRECPS, INS_SVE_FRECPS} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ReverseBits, -1, 1, true, {INS_SVE_RBIT, INS_SVE_RBIT, INS_SVE_RBIT, INS_SVE_RBIT, INS_SVE_RBIT, INS_SVE_RBIT, INS_SVE_RBIT, INS_SVE_RBIT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ReverseBytesWithinElements, -1, 1, true, {INS_invalid, INS_invalid, INS_SVE_REVB, INS_SVE_REVB, INS_SVE_REVB, INS_SVE_REVB, INS_SVE_REVB, INS_SVE_REVB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ReverseElement, -1, 1, true, {INS_SVE_REV, INS_SVE_REV, INS_SVE_REV, INS_SVE_REV, INS_SVE_REV, INS_SVE_REV, INS_SVE_REV, INS_SVE_REV, INS_SVE_REV, INS_SVE_REV} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ReverseInt16WithinElements, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_REVH, INS_SVE_REVH, INS_SVE_REVH, INS_SVE_REVH, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ReverseInt32WithinElements, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_REVW, INS_SVE_REVW, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, RoundAwayFromZero, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FRINTA, INS_SVE_FRINTA} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, RoundToNearest, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FRINTN, INS_SVE_FRINTN} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, RoundToNegativeInfinity, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FRINTM, INS_SVE_FRINTM} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, RoundToPositiveInfinity, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FRINTP, INS_SVE_FRINTP} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, RoundToZero, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FRINTZ, INS_SVE_FRINTZ} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, SaturatingDecrementByActiveElementCount, -1, 2, true, {INS_invalid, INS_SVE_SQDECP/INS_SVE_UQDECP,INS_SVE_SQDECP, INS_SVE_SQDECP/INS_SVE_UQDECP,INS_SVE_SQDECP, INS_SVE_SQDECP/INS_SVE_UQDECP,INS_SVE_SQDECP, INS_SVE_SQDECP/INS_SVE_UQDECP,INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, SaturatingDecrementByteElementCount, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, SaturatingDecrementInt16ElementCount, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SQDECH, INS_SVE_UQDECH, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, SaturatingDecrementInt32ElementCount, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SQDECW, INS_SVE_UQDECW, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, SaturatingDecrementInt64ElementCount, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SQDECD, INS_SVE_UQDECD, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, SaturatingIncrementByActiveElementCount, -1, 2, true, {INS_invalid, INS_SVE_SQINCP/INS_SVE_UQINCP,INS_SVE_SQINCP, INS_SVE_SQINCP/INS_SVE_UQINCP,INS_SVE_SQINCP, INS_SVE_SQINCP/INS_SVE_UQINCP,INS_SVE_SQINCP, INS_SVE_SQINCP/INS_SVE_UQINCP,INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, SaturatingIncrementByteElementCount, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, SaturatingIncrementInt16ElementCount, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SQINCH, INS_SVE_UQINCH, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, SaturatingIncrementInt32ElementCount, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SQINCW, INS_SVE_UQINCW, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, SaturatingIncrementInt64ElementCount, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SQINCD, INS_SVE_UQINCD, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, Scale, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FSCALE, INS_SVE_FSCALE} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve, Scatter, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1W, INS_SVE_ST1W, INS_SVE_ST1D, INS_SVE_ST1D, INS_SVE_ST1W, INS_SVE_ST1D} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ScatterInt32NarrowToInt16, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1H, INS_SVE_ST1H, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ScatterInt32NarrowToSByte, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1B, INS_SVE_ST1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ScatterInt64NarrowToInt16, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1H, INS_SVE_ST1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ScatterInt64NarrowToInt32, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1W, INS_SVE_ST1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ScatterInt64NarrowToSByte, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1B, INS_SVE_ST1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ScatterTruncate16UInt16, -1, 4, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1H, INS_SVE_ST1H, INS_SVE_ST1H, INS_SVE_ST1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ScatterTruncate32UInt32, -1, 4, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1W, INS_SVE_ST1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ScatterTruncate8Byte, -1, 4, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1B, INS_SVE_ST1B, INS_SVE_ST1B, INS_SVE_ST1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve, ScatterUInt32NarrowToByte, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1B, INS_SVE_ST1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ScatterUInt32NarrowToUInt16, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1H, INS_SVE_ST1H, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ScatterUInt64NarrowToByte, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1B, INS_SVE_ST1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ScatterUInt64NarrowToUInt16, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1H, INS_SVE_ST1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ScatterUInt64NarrowToUInt32, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1W, INS_SVE_ST1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, SetFFR, -1, 0, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ShiftLeftLogical, -1, 2, true, {INS_SVE_LSL, INS_SVE_LSL, INS_SVE_LSL, INS_SVE_LSL, INS_SVE_LSL, INS_SVE_LSL, INS_SVE_LSL, INS_SVE_LSL, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ShiftRightArithmetic, -1, 2, true, {INS_SVE_ASR, INS_invalid, INS_SVE_ASR, INS_invalid, INS_SVE_ASR, INS_invalid, INS_SVE_ASR, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, ShiftRightArithmeticDivide, -1, 2, true, {INS_SVE_ASRD, INS_invalid, INS_SVE_ASRD, INS_invalid, INS_SVE_ASRD, INS_invalid, INS_SVE_ASRD, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ShiftRightLogical, -1, 2, true, {INS_invalid, INS_SVE_LSR, INS_invalid, INS_SVE_LSR, INS_invalid, INS_SVE_LSR, INS_invalid, INS_SVE_LSR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, SignExtend16, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SXTH, INS_invalid, INS_SVE_SXTH, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, SignExtend32, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SXTW, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, SignExtend8, -1, 1, true, {INS_invalid, INS_invalid, INS_SVE_SXTB, INS_invalid, INS_SVE_SXTB, INS_invalid, INS_SVE_SXTB, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, SignExtendWideningLower, -1, 1, true, {INS_invalid, INS_invalid, INS_SVE_SUNPKLO, INS_invalid, INS_SVE_SUNPKLO, INS_invalid, INS_SVE_SUNPKLO, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve, SignExtendWideningUpper, -1, 1, true, {INS_invalid, INS_invalid, INS_SVE_SUNPKHI, INS_invalid, INS_SVE_SUNPKHI, INS_invalid, INS_SVE_SUNPKHI, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve, Splice, -1, 3, true, {INS_SVE_SPLICE, INS_SVE_SPLICE, INS_SVE_SPLICE, INS_SVE_SPLICE, INS_SVE_SPLICE, INS_SVE_SPLICE, INS_SVE_SPLICE, INS_SVE_SPLICE, INS_SVE_SPLICE, INS_SVE_SPLICE} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Sqrt, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FSQRT, INS_SVE_FSQRT} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Store, -1, 3, true, {INS_SVE_ST1B, INS_SVE_ST1B, INS_SVE_ST1H, INS_SVE_ST1H, INS_SVE_ST1W, INS_SVE_ST1W, INS_SVE_ST1D, INS_SVE_ST1D, INS_SVE_ST1W, INS_SVE_ST1D} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreInt16NarrowToSByte, -1, 3, false, {INS_invalid, INS_invalid, INS_SVE_ST1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreInt32NarrowToInt16, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1H, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreInt32NarrowToSByte, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreInt64NarrowToInt16, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1H, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreInt64NarrowToInt32, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1W, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreInt64NarrowToSByte, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1B, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreNonTemporal, -1, 3, true, {INS_SVE_STNT1B, INS_SVE_STNT1B, INS_SVE_STNT1H, INS_SVE_STNT1H, INS_SVE_STNT1W, INS_SVE_STNT1W, INS_SVE_STNT1D, INS_SVE_STNT1D, INS_SVE_STNT1W, INS_SVE_STNT1D} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreUInt16NarrowToByte, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreUInt32NarrowToByte, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreUInt32NarrowToUInt16, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1H, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreUInt64NarrowToByte, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreUInt64NarrowToUInt16, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, StoreUInt64NarrowToUInt32, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ST1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Storex2, -1, 3, true, {INS_SVE_ST2B, INS_SVE_ST2B, INS_SVE_ST2H, INS_SVE_ST2H, INS_SVE_ST2W, INS_SVE_ST2W, INS_SVE_ST2D, INS_SVE_ST2D, INS_SVE_ST2W, INS_SVE_ST2D} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Storex3, -1, 3, true, {INS_SVE_ST3B, INS_SVE_ST3B, INS_SVE_ST3H, INS_SVE_ST3H, INS_SVE_ST3W, INS_SVE_ST3W, INS_SVE_ST3D, INS_SVE_ST3D, INS_SVE_ST3W, INS_SVE_ST3D} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Storex4, -1, 3, true, {INS_SVE_ST4B, INS_SVE_ST4B, INS_SVE_ST4H, INS_SVE_ST4H, INS_SVE_ST4W, INS_SVE_ST4W, INS_SVE_ST4D, INS_SVE_ST4D, INS_SVE_ST4W, INS_SVE_ST4D} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Subtract, -1, 2, true, {INS_SVE_SUB, INS_SVE_SUB, INS_SVE_SUB, INS_SVE_SUB, INS_SVE_SUB, INS_SVE_SUB, INS_SVE_SUB, INS_SVE_SUB, INS_SVE_FSUB, INS_SVE_FSUB} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, SubtractReversed, -1, 2, true, {INS_SVE_SUBR, INS_SVE_SUBR, INS_SVE_SUBR, INS_SVE_SUBR, INS_SVE_SUBR, INS_SVE_SUBR, INS_SVE_SUBR, INS_SVE_SUBR, INS_SVE_FSUBR, INS_SVE_FSUBR} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, SubtractSaturate, -1, 2, true, {INS_SVE_SQSUB, INS_SVE_UQSUB, INS_SVE_SQSUB, INS_SVE_UQSUB, INS_SVE_SQSUB, INS_SVE_UQSUB, INS_SVE_SQSUB, INS_SVE_UQSUB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, TransposeEven, -1, 2, true, {INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, TransposeOdd, -1, 2, true, {INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, TrigonometricMultiplyAddCoefficient, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FTMAD, INS_SVE_FTMAD} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, TrigonometricSelectCoefficient, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FTSSEL, INS_SVE_FTSSEL} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve, TrigonometricStartingValue, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FTSMUL, INS_SVE_FTSMUL} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve, TrueMask, -1, 0, false, {INS_invalid, INS_SVE_PTRUE, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, UnzipEven, -1, 2, true, {INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, UnzipOdd, -1, 2, true, {INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, VectorTableLookup, -1, 2, true, {INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve, WriteFFR, -1, 1, true, {INS_SVE_WRFFR, INS_SVE_WRFFR, INS_SVE_WRFFR, INS_SVE_WRFFR, INS_SVE_WRFFR, INS_SVE_WRFFR, INS_SVE_WRFFR, INS_SVE_WRFFR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, Xor, -1, 2, true, {INS_SVE_EOR, INS_SVE_EOR, INS_SVE_EOR, INS_SVE_EOR, INS_SVE_EOR, INS_SVE_EOR, INS_SVE_EOR, INS_SVE_EOR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, XorAcross, -1, 1, true, {INS_SVE_EORV, INS_SVE_EORV, INS_SVE_EORV, INS_SVE_EORV, INS_SVE_EORV, INS_SVE_EORV, INS_SVE_EORV, INS_SVE_EORV, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ZeroExtend16, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_UXTH, INS_invalid, INS_SVE_UXTH, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ZeroExtend32, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_UXTW, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ZeroExtend8, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_UXTB, INS_invalid, INS_SVE_UXTB, INS_invalid, INS_SVE_UXTB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ZeroExtendWideningLower, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_UUNPKLO, INS_invalid, INS_SVE_UUNPKLO, INS_invalid, INS_SVE_UUNPKLO, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve, ZeroExtendWideningUpper, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_UUNPKHI, INS_invalid, INS_SVE_UUNPKHI, INS_invalid, INS_SVE_UUNPKHI, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve, ZipHigh, -1, 2, true, {INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve, ZipLow, -1, 2, true, {INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1} HW_Category_SIMD, HW_Flag_NoFlag)
+
+
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags
+// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// Sve2
+HARDWARE_INTRINSIC(Sve2, AbsoluteDifferenceAdd, -1, 3, true, {INS_SVE_SABA, INS_SVE_UABA, INS_SVE_SABA, INS_SVE_UABA, INS_SVE_SABA, INS_SVE_UABA, INS_SVE_SABA, INS_SVE_UABA, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, AbsoluteDifferenceAddWideningLower, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_SABALB, INS_SVE_UABALB, INS_SVE_SABALB, INS_SVE_UABALB, INS_SVE_SABALB, INS_SVE_UABALB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AbsoluteDifferenceAddWideningUpper, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_SABALT, INS_SVE_UABALT, INS_SVE_SABALT, INS_SVE_UABALT, INS_SVE_SABALT, INS_SVE_UABALT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AbsoluteDifferenceWideningLower, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SABDLB, INS_SVE_UABDLB, INS_SVE_SABDLB, INS_SVE_UABDLB, INS_SVE_SABDLB, INS_SVE_UABDLB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AbsoluteDifferenceWideningUpper, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SABDLT, INS_SVE_UABDLT, INS_SVE_SABDLT, INS_SVE_UABDLT, INS_SVE_SABDLT, INS_SVE_UABDLT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AddCarryWideningLower, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ADCLB, INS_invalid, INS_SVE_ADCLB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, AddCarryWideningUpper, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_ADCLT, INS_invalid, INS_SVE_ADCLT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, AddHighNarowingLower, -1, 2, true, {INS_SVE_ADDHNB, INS_SVE_ADDHNB, INS_SVE_ADDHNB, INS_SVE_ADDHNB, INS_SVE_ADDHNB, INS_SVE_ADDHNB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AddHighNarowingUpper, -1, 3, true, {INS_SVE_ADDHNT, INS_SVE_ADDHNT, INS_SVE_ADDHNT, INS_SVE_ADDHNT, INS_SVE_ADDHNT, INS_SVE_ADDHNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AddPairwise, -1, 2, true, {INS_SVE_ADDP, INS_SVE_ADDP, INS_SVE_ADDP, INS_SVE_ADDP, INS_SVE_ADDP, INS_SVE_ADDP, INS_SVE_ADDP, INS_SVE_ADDP, INS_SVE_FADDP, INS_SVE_FADDP} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, AddPairwiseWidening, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SADALP, INS_SVE_UADALP, INS_SVE_SADALP, INS_SVE_UADALP, INS_SVE_SADALP, INS_SVE_UADALP, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AddRotateComplex, -1, 3, true, {INS_SVE_CADD, INS_SVE_CADD, INS_SVE_CADD, INS_SVE_CADD, INS_SVE_CADD, INS_SVE_CADD, INS_SVE_CADD, INS_SVE_CADD, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, AddSaturate, -1, 2, true, {INS_SVE_SQADD, INS_SVE_UQADD, INS_SVE_SQADD, INS_SVE_UQADD, INS_SVE_SQADD, INS_SVE_UQADD, INS_SVE_SQADD, INS_SVE_UQADD, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, AddSaturateWithSignedAddend, -1, 2, true, {INS_invalid, INS_SVE_USQADD, INS_invalid, INS_SVE_USQADD, INS_invalid, INS_SVE_USQADD, INS_invalid, INS_SVE_USQADD, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AddSaturateWithUnsignedAddend, -1, 2, true, {INS_SVE_SUQADD, INS_invalid, INS_SVE_SUQADD, INS_invalid, INS_SVE_SUQADD, INS_invalid, INS_SVE_SUQADD, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AddWideLower, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SADDWB, INS_SVE_UADDWB, INS_SVE_SADDWB, INS_SVE_UADDWB, INS_SVE_SADDWB, INS_SVE_UADDWB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AddWideUpper, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SADDWT, INS_SVE_UADDWT, INS_SVE_SADDWT, INS_SVE_UADDWT, INS_SVE_SADDWT, INS_SVE_UADDWT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AddWideningLower, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SADDLB, INS_SVE_UADDLB, INS_SVE_SADDLB, INS_SVE_UADDLB, INS_SVE_SADDLB, INS_SVE_UADDLB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AddWideningLowerUpper, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SADDLBT, INS_invalid, INS_SVE_SADDLBT, INS_invalid, INS_SVE_SADDLBT, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, AddWideningUpper, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SADDLT, INS_SVE_UADDLT, INS_SVE_SADDLT, INS_SVE_UADDLT, INS_SVE_SADDLT, INS_SVE_UADDLT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, BitwiseClearXor, -1, 3, true, {INS_SVE_BCAX, INS_SVE_BCAX, INS_SVE_BCAX, INS_SVE_BCAX, INS_SVE_BCAX, INS_SVE_BCAX, INS_SVE_BCAX, INS_SVE_BCAX, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, BitwiseSelect, -1, 3, true, {INS_SVE_BSL, INS_SVE_BSL, INS_SVE_BSL, INS_SVE_BSL, INS_SVE_BSL, INS_SVE_BSL, INS_SVE_BSL, INS_SVE_BSL, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, BitwiseSelectFirstInverted, -1, 3, true, {INS_SVE_BSL1N, INS_SVE_BSL1N, INS_SVE_BSL1N, INS_SVE_BSL1N, INS_SVE_BSL1N, INS_SVE_BSL1N, INS_SVE_BSL1N, INS_SVE_BSL1N, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, BitwiseSelectInverted, -1, 3, true, {INS_SVE_NBSL, INS_SVE_NBSL, INS_SVE_NBSL, INS_SVE_NBSL, INS_SVE_NBSL, INS_SVE_NBSL, INS_SVE_NBSL, INS_SVE_NBSL, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, BitwiseSelectSecondInverted, -1, 3, true, {INS_SVE_BSL2N, INS_SVE_BSL2N, INS_SVE_BSL2N, INS_SVE_BSL2N, INS_SVE_BSL2N, INS_SVE_BSL2N, INS_SVE_BSL2N, INS_SVE_BSL2N, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, CountMatchingElements, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_HISTCNT, INS_invalid, INS_SVE_HISTCNT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, CountMatchingElementsIn128BitSegments, -1, 2, false, {INS_invalid, INS_SVE_HISTSEG, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, CreateWhileGreaterThanMask, -1, 2, true, {INS_invalid, INS_SVE_WHILEGT/INS_SVE_WHILEHI,INS_invalid, INS_SVE_WHILEGT/INS_SVE_WHILEHI,INS_invalid, INS_SVE_WHILEGT/INS_SVE_WHILEHI,INS_invalid, INS_SVE_WHILEGT/INS_SVE_WHILEHI,INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, CreateWhileGreaterThanOrEqualMask, -1, 2, true, {INS_invalid, INS_SVE_WHILEGE/INS_SVE_WHILEHS,INS_invalid, INS_SVE_WHILEGE/INS_SVE_WHILEHS,INS_invalid, INS_SVE_WHILEGE/INS_SVE_WHILEHS,INS_invalid, INS_SVE_WHILEGE/INS_SVE_WHILEHS,INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, CreateWhileReadAfterWriteMask, -1, 2, true, {INS_SVE_WHILERW, INS_SVE_WHILERW, INS_SVE_WHILERW, INS_SVE_WHILERW, INS_SVE_WHILERW, INS_SVE_WHILERW, INS_SVE_WHILERW, INS_SVE_WHILERW, INS_SVE_WHILERW, INS_SVE_WHILERW} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, CreateWhileWriteAfterReadMask, -1, 2, true, {INS_SVE_WHILEWR, INS_SVE_WHILEWR, INS_SVE_WHILEWR, INS_SVE_WHILEWR, INS_SVE_WHILEWR, INS_SVE_WHILEWR, INS_SVE_WHILEWR, INS_SVE_WHILEWR, INS_SVE_WHILEWR, INS_SVE_WHILEWR} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, DotProductComplex, -1, 4, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_CDOT, INS_invalid, INS_SVE_CDOT, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, DownConvertNarrowingUpper, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTNT, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, DownConvertRoundingOdd, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTX, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, DownConvertRoundingOddUpper, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTXNT, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, GatherVectorByteSignExtendNonTemporal, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNT1SB, INS_SVE_LDNT1SB, INS_SVE_LDNT1SB, INS_SVE_LDNT1SB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, GatherVectorByteZeroExtendNonTemporal, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNT1B, INS_SVE_LDNT1B, INS_SVE_LDNT1B, INS_SVE_LDNT1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, GatherVectorInt16SignExtendNonTemporal, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNT1SH, INS_SVE_LDNT1SH, INS_SVE_LDNT1SH, INS_SVE_LDNT1SH, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, GatherVectorInt16ZeroExtendNonTemporal, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNT1H, INS_SVE_LDNT1H, INS_SVE_LDNT1H, INS_SVE_LDNT1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, GatherVectorInt32SignExtendNonTemporal, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNT1SW, INS_SVE_LDNT1SW, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, GatherVectorInt32ZeroExtendNonTemporal, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNT1W, INS_SVE_LDNT1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, GatherVectorNonTemporal, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_LDNT1W, INS_SVE_LDNT1W, INS_SVE_LDNT1D, INS_SVE_LDNT1D, INS_SVE_LDNT1W, INS_SVE_LDNT1D} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, HalvingAdd, -1, 2, true, {INS_SVE_SHADD, INS_SVE_UHADD, INS_SVE_SHADD, INS_SVE_UHADD, INS_SVE_SHADD, INS_SVE_UHADD, INS_SVE_SHADD, INS_SVE_UHADD, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, HalvingSubtract, -1, 2, true, {INS_SVE_SHSUB, INS_SVE_UHSUB, INS_SVE_SHSUB, INS_SVE_UHSUB, INS_SVE_SHSUB, INS_SVE_UHSUB, INS_SVE_SHSUB, INS_SVE_UHSUB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, HalvingSubtractReversed, -1, 2, true, {INS_SVE_SHSUBR, INS_SVE_UHSUBR, INS_SVE_SHSUBR, INS_SVE_UHSUBR, INS_SVE_SHSUBR, INS_SVE_UHSUBR, INS_SVE_SHSUBR, INS_SVE_UHSUBR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, InterleavingXorLowerUpper, -1, 3, true, {INS_SVE_EORBT, INS_SVE_EORBT, INS_SVE_EORBT, INS_SVE_EORBT, INS_SVE_EORBT, INS_SVE_EORBT, INS_SVE_EORBT, INS_SVE_EORBT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, InterleavingXorUpperLower, -1, 3, true, {INS_SVE_EORTB, INS_SVE_EORTB, INS_SVE_EORTB, INS_SVE_EORTB, INS_SVE_EORTB, INS_SVE_EORTB, INS_SVE_EORTB, INS_SVE_EORTB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, Log2, -1, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FLOGB, INS_invalid, INS_SVE_FLOGB, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, Match, -1, 3, true, {INS_SVE_MATCH, INS_SVE_MATCH, INS_SVE_MATCH, INS_SVE_MATCH, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, MaxNumberPairwise, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMAXNMP, INS_SVE_FMAXNMP} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, MaxPairwise, -1, 2, true, {INS_SVE_SMAXP, INS_SVE_UMAXP, INS_SVE_SMAXP, INS_SVE_UMAXP, INS_SVE_SMAXP, INS_SVE_UMAXP, INS_SVE_SMAXP, INS_SVE_UMAXP, INS_SVE_FMAXP, INS_SVE_FMAXP} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, MinNumberPairwise, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMINNMP, INS_SVE_FMINNMP} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, MinPairwise, -1, 2, true, {INS_SVE_SMINP, INS_SVE_UMINP, INS_SVE_SMINP, INS_SVE_UMINP, INS_SVE_SMINP, INS_SVE_UMINP, INS_SVE_SMINP, INS_SVE_UMINP, INS_SVE_FMINP, INS_SVE_FMINP} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, MoveWideningLower, -1, 1, true, {INS_invalid, INS_invalid, INS_SVE_SSHLLB, INS_SVE_USHLLB, INS_SVE_SSHLLB, INS_SVE_USHLLB, INS_SVE_SSHLLB, INS_SVE_USHLLB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, MoveWideningUpper, -1, 1, true, {INS_invalid, INS_invalid, INS_SVE_SSHLLT, INS_SVE_USHLLT, INS_SVE_SSHLLT, INS_SVE_USHLLT, INS_SVE_SSHLLT, INS_SVE_USHLLT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, Multiply, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_MUL, INS_SVE_MUL, INS_SVE_MUL, INS_SVE_MUL, INS_SVE_MUL, INS_SVE_MUL, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, MultiplyAdd, -1, 4, true, {INS_invalid, INS_invalid, INS_SVE_MLA, INS_SVE_MLA, INS_SVE_MLA, INS_SVE_MLA, INS_SVE_MLA, INS_SVE_MLA, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, MultiplyAddRotateComplex, -1, 4, true, {INS_SVE_CMLA, INS_SVE_CMLA, INS_SVE_CMLA, INS_SVE_CMLA, INS_SVE_CMLA, INS_SVE_CMLA, INS_SVE_CMLA, INS_SVE_CMLA, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, MultiplyAddWideningLower, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_SMLALB, INS_SVE_UMLALB, INS_SVE_SMLALB, INS_SVE_UMLALB, INS_SVE_SMLALB, INS_SVE_UMLALB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, MultiplyAddWideningUpper, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_SMLALT, INS_SVE_UMLALT, INS_SVE_SMLALT, INS_SVE_UMLALT, INS_SVE_SMLALT, INS_SVE_UMLALT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, MultiplySubtract, -1, 4, true, {INS_invalid, INS_invalid, INS_SVE_MLS, INS_SVE_MLS, INS_SVE_MLS, INS_SVE_MLS, INS_SVE_MLS, INS_SVE_MLS, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, MultiplySubtractWideningLower, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_SMLSLB, INS_SVE_UMLSLB, INS_SVE_SMLSLB, INS_SVE_UMLSLB, INS_SVE_SMLSLB, INS_SVE_UMLSLB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, MultiplySubtractWideningUpper, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_SMLSLT, INS_SVE_UMLSLT, INS_SVE_SMLSLT, INS_SVE_UMLSLT, INS_SVE_SMLSLT, INS_SVE_UMLSLT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, MultiplyWideningLower, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SMULLB, INS_SVE_UMULLB, INS_SVE_SMULLB, INS_SVE_UMULLB, INS_SVE_SMULLB, INS_SVE_UMULLB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, MultiplyWideningUpper, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SMULLT, INS_SVE_UMULLT, INS_SVE_SMULLT, INS_SVE_UMULLT, INS_SVE_SMULLT, INS_SVE_UMULLT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, NoMatch, -1, 3, true, {INS_SVE_NMATCH, INS_SVE_NMATCH, INS_SVE_NMATCH, INS_SVE_NMATCH, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, PolynomialMultiply, -1, 2, false, {INS_invalid, INS_SVE_PMUL, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, PolynomialMultiplyWideningLower, -1, 2, true, {INS_invalid, INS_SVE_PMULLB, INS_invalid, INS_SVE_PMULLB, INS_invalid, INS_SVE_PMULLB, INS_invalid, INS_SVE_PMULLB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, PolynomialMultiplyWideningUpper, -1, 2, true, {INS_invalid, INS_SVE_PMULLT, INS_invalid, INS_SVE_PMULLT, INS_invalid, INS_SVE_PMULLT, INS_invalid, INS_SVE_PMULLT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, ReciprocalEstimate, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_URECPE, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, ReciprocalSqrtEstimate, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_URSQRTE, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, RoundingAddHighNarowingLower, -1, 2, true, {INS_SVE_RADDHNB, INS_SVE_RADDHNB, INS_SVE_RADDHNB, INS_SVE_RADDHNB, INS_SVE_RADDHNB, INS_SVE_RADDHNB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, RoundingAddHighNarowingUpper, -1, 3, true, {INS_SVE_RADDHNT, INS_SVE_RADDHNT, INS_SVE_RADDHNT, INS_SVE_RADDHNT, INS_SVE_RADDHNT, INS_SVE_RADDHNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, RoundingHalvingAdd, -1, 2, true, {INS_SVE_SRHADD, INS_SVE_URHADD, INS_SVE_SRHADD, INS_SVE_URHADD, INS_SVE_SRHADD, INS_SVE_URHADD, INS_SVE_SRHADD, INS_SVE_URHADD, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, RoundingShiftLeft, -1, 2, true, {INS_SVE_SRSHL, INS_SVE_URSHL, INS_SVE_SRSHL, INS_SVE_URSHL, INS_SVE_SRSHL, INS_SVE_URSHL, INS_SVE_SRSHL, INS_SVE_URSHL, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, RoundingShiftRight, -1, 2, true, {INS_SVE_SRSHR, INS_SVE_URSHR, INS_SVE_SRSHR, INS_SVE_URSHR, INS_SVE_SRSHR, INS_SVE_URSHR, INS_SVE_SRSHR, INS_SVE_URSHR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, RoundingShiftRightAndAccumulate, -1, 3, true, {INS_SVE_SRSRA, INS_SVE_URSRA, INS_SVE_SRSRA, INS_SVE_URSRA, INS_SVE_SRSRA, INS_SVE_URSRA, INS_SVE_SRSRA, INS_SVE_URSRA, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, RoundingShiftRightNarrowingLower, -1, 2, true, {INS_SVE_RSHRNB, INS_SVE_RSHRNB, INS_SVE_RSHRNB, INS_SVE_RSHRNB, INS_SVE_RSHRNB, INS_SVE_RSHRNB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, RoundingShiftRightNarrowingUpper, -1, 3, true, {INS_SVE_RSHRNT, INS_SVE_RSHRNT, INS_SVE_RSHRNT, INS_SVE_RSHRNT, INS_SVE_RSHRNT, INS_SVE_RSHRNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, RoundingSubtractHighNarowingLower, -1, 2, true, {INS_SVE_RSUBHNB, INS_SVE_RSUBHNB, INS_SVE_RSUBHNB, INS_SVE_RSUBHNB, INS_SVE_RSUBHNB, INS_SVE_RSUBHNB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, RoundingSubtractHighNarowingUpper, -1, 3, true, {INS_SVE_RSUBHNT, INS_SVE_RSUBHNT, INS_SVE_RSUBHNT, INS_SVE_RSUBHNT, INS_SVE_RSUBHNT, INS_SVE_RSUBHNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingAbs, -1, 1, true, {INS_SVE_SQABS, INS_invalid, INS_SVE_SQABS, INS_invalid, INS_SVE_SQABS, INS_invalid, INS_SVE_SQABS, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, SaturatingComplexAddRotate, -1, 3, true, {INS_SVE_SQCADD, INS_invalid, INS_SVE_SQCADD, INS_invalid, INS_SVE_SQCADD, INS_invalid, INS_SVE_SQCADD, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, SaturatingDoublingMultiplyAddWideningLower, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_SQDMLALB, INS_invalid, INS_SVE_SQDMLALB, INS_invalid, INS_SVE_SQDMLALB, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, SaturatingDoublingMultiplyAddWideningLowerUpper, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_SQDMLALBT, INS_invalid, INS_SVE_SQDMLALBT, INS_invalid, INS_SVE_SQDMLALBT, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingDoublingMultiplyAddWideningUpper, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_SQDMLALT, INS_invalid, INS_SVE_SQDMLALT, INS_invalid, INS_SVE_SQDMLALT, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, SaturatingDoublingMultiplyHigh, -1, 2, true, {INS_SVE_SQDMULH, INS_invalid, INS_SVE_SQDMULH, INS_invalid, INS_SVE_SQDMULH, INS_invalid, INS_SVE_SQDMULH, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, SaturatingDoublingMultiplySubtractWideningLower, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_SQDMLSLB, INS_invalid, INS_SVE_SQDMLSLB, INS_invalid, INS_SVE_SQDMLSLB, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, SaturatingDoublingMultiplySubtractWideningLowerUpper, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_SQDMLSLBT, INS_invalid, INS_SVE_SQDMLSLBT, INS_invalid, INS_SVE_SQDMLSLBT, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingDoublingMultiplySubtractWideningUpper, -1, 3, true, {INS_invalid, INS_invalid, INS_SVE_SQDMLSLT, INS_invalid, INS_SVE_SQDMLSLT, INS_invalid, INS_SVE_SQDMLSLT, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, SaturatingDoublingMultiplyWideningLower, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SQDMULLB, INS_invalid, INS_SVE_SQDMULLB, INS_invalid, INS_SVE_SQDMULLB, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, SaturatingDoublingMultiplyWideningUpper, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SQDMULLT, INS_invalid, INS_SVE_SQDMULLT, INS_invalid, INS_SVE_SQDMULLT, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, SaturatingExtractNarrowingLower, -1, 1, true, {INS_SVE_SQXTNB, INS_SVE_UQXTNB, INS_SVE_SQXTNB, INS_SVE_UQXTNB, INS_SVE_SQXTNB, INS_SVE_UQXTNB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingExtractNarrowingUpper, -1, 2, true, {INS_SVE_SQXTNT, INS_SVE_UQXTNT, INS_SVE_SQXTNT, INS_SVE_UQXTNT, INS_SVE_SQXTNT, INS_SVE_UQXTNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingExtractUnsignedNarrowingLower, -1, 1, true, {INS_invalid, INS_SVE_SQXTUNB, INS_invalid, INS_SVE_SQXTUNB, INS_invalid, INS_SVE_SQXTUNB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingExtractUnsignedNarrowingUpper, -1, 2, true, {INS_invalid, INS_SVE_SQXTUNT, INS_invalid, INS_SVE_SQXTUNT, INS_invalid, INS_SVE_SQXTUNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingNegate, -1, 1, true, {INS_SVE_SQNEG, INS_invalid, INS_SVE_SQNEG, INS_invalid, INS_SVE_SQNEG, INS_invalid, INS_SVE_SQNEG, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, SaturatingRoundingDoublingComplexMultiplyAddHighRotate, -1, 4, true, {INS_SVE_SQRDCMLAH, INS_invalid, INS_SVE_SQRDCMLAH, INS_invalid, INS_SVE_SQRDCMLAH, INS_invalid, INS_SVE_SQRDCMLAH, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, SaturatingRoundingDoublingMultiplyAddHigh, -1, 3, true, {INS_SVE_SQRDMLAH, INS_invalid, INS_SVE_SQRDMLAH, INS_invalid, INS_SVE_SQRDMLAH, INS_invalid, INS_SVE_SQRDMLAH, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, SaturatingRoundingDoublingMultiplyHigh, -1, 2, true, {INS_SVE_SQRDMULH, INS_invalid, INS_SVE_SQRDMULH, INS_invalid, INS_SVE_SQRDMULH, INS_invalid, INS_SVE_SQRDMULH, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, SaturatingRoundingDoublingMultiplySubtractHigh, -1, 3, true, {INS_SVE_SQRDMLSH, INS_invalid, INS_SVE_SQRDMLSH, INS_invalid, INS_SVE_SQRDMLSH, INS_invalid, INS_SVE_SQRDMLSH, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, SaturatingRoundingShiftLeft, -1, 2, true, {INS_SVE_SQRSHL, INS_SVE_UQRSHL, INS_SVE_SQRSHL, INS_SVE_UQRSHL, INS_SVE_SQRSHL, INS_SVE_UQRSHL, INS_SVE_SQRSHL, INS_SVE_UQRSHL, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingRoundingShiftRightNarrowingLower, -1, 2, true, {INS_SVE_SQRSHRNB, INS_SVE_UQRSHRNB, INS_SVE_SQRSHRNB, INS_SVE_UQRSHRNB, INS_SVE_SQRSHRNB, INS_SVE_UQRSHRNB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingRoundingShiftRightNarrowingUpper, -1, 3, true, {INS_SVE_SQRSHRNT, INS_SVE_UQRSHRNT, INS_SVE_SQRSHRNT, INS_SVE_UQRSHRNT, INS_SVE_SQRSHRNT, INS_SVE_UQRSHRNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingRoundingShiftRightUnsignedNarrowingLower, -1, 2, true, {INS_invalid, INS_SVE_SQRSHRUNB, INS_invalid, INS_SVE_SQRSHRUNB, INS_invalid, INS_SVE_SQRSHRUNB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingRoundingShiftRightUnsignedNarrowingUpper, -1, 3, true, {INS_invalid, INS_SVE_SQRSHRUNT, INS_invalid, INS_SVE_SQRSHRUNT, INS_invalid, INS_SVE_SQRSHRUNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingShiftLeft, -1, 2, true, {INS_SVE_SQSHL, INS_SVE_UQSHL, INS_SVE_SQSHL, INS_SVE_UQSHL, INS_SVE_SQSHL, INS_SVE_UQSHL, INS_SVE_SQSHL, INS_SVE_UQSHL, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingShiftLeftUnsigned, -1, 2, true, {INS_invalid, INS_SVE_SQSHLU, INS_invalid, INS_SVE_SQSHLU, INS_invalid, INS_SVE_SQSHLU, INS_invalid, INS_SVE_SQSHLU, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingShiftRightNarrowingLower, -1, 2, true, {INS_SVE_SQSHRNB, INS_SVE_UQSHRNB, INS_SVE_SQSHRNB, INS_SVE_UQSHRNB, INS_SVE_SQSHRNB, INS_SVE_UQSHRNB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingShiftRightNarrowingUpper, -1, 3, true, {INS_SVE_SQSHRNT, INS_SVE_UQSHRNT, INS_SVE_SQSHRNT, INS_SVE_UQSHRNT, INS_SVE_SQSHRNT, INS_SVE_UQSHRNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingShiftRightUnsignedNarrowingLower, -1, 2, true, {INS_invalid, INS_SVE_SQSHRUNB, INS_invalid, INS_SVE_SQSHRUNB, INS_invalid, INS_SVE_SQSHRUNB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SaturatingShiftRightUnsignedNarrowingUpper, -1, 3, true, {INS_invalid, INS_SVE_SQSHRUNT, INS_invalid, INS_SVE_SQSHRUNT, INS_invalid, INS_SVE_SQSHRUNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, ScatterInt32NarrowToInt16, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1H, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, ScatterInt32NarrowToSByte, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, ScatterInt64NarrowToInt16, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1H, INS_SVE_STNT1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, ScatterInt64NarrowToInt32, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1W, INS_SVE_STNT1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, ScatterInt64NarrowToSByte, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1B, INS_SVE_STNT1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, ScatterNonTemporal, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1W, INS_SVE_STNT1W, INS_SVE_STNT1D, INS_SVE_STNT1D, INS_SVE_STNT1W, INS_SVE_STNT1D} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, ScatterTruncate16NonTemporalUInt16, -1, 4, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1H, INS_SVE_STNT1H, INS_SVE_STNT1H, INS_SVE_STNT1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, ScatterTruncate32NonTemporalUInt32, -1, 4, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1W, INS_SVE_STNT1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, ScatterTruncate8NonTemporalByte, -1, 4, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1B, INS_SVE_STNT1B, INS_SVE_STNT1B, INS_SVE_STNT1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, ScatterUInt32NarrowToByte, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1B, INS_SVE_STNT1B, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, ScatterUInt32NarrowToUInt16, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1H, INS_SVE_STNT1H, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, ScatterUInt64NarrowToByte, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1B, INS_SVE_STNT1B, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, ScatterUInt64NarrowToUInt16, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1H, INS_SVE_STNT1H, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, ScatterUInt64NarrowToUInt32, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_STNT1W, INS_SVE_STNT1W, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve2, ShiftLeftAndInsert, -1, 3, true, {INS_SVE_SLI, INS_SVE_SLI, INS_SVE_SLI, INS_SVE_SLI, INS_SVE_SLI, INS_SVE_SLI, INS_SVE_SLI, INS_SVE_SLI, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, ShiftLeftWideningLower, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SSHLLB, INS_SVE_USHLLB, INS_SVE_SSHLLB, INS_SVE_USHLLB, INS_SVE_SSHLLB, INS_SVE_USHLLB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, ShiftLeftWideningUpper, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SSHLLT, INS_SVE_USHLLT, INS_SVE_SSHLLT, INS_SVE_USHLLT, INS_SVE_SSHLLT, INS_SVE_USHLLT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, ShiftRightAndAccumulate, -1, 3, true, {INS_SVE_SSRA, INS_SVE_USRA, INS_SVE_SSRA, INS_SVE_USRA, INS_SVE_SSRA, INS_SVE_USRA, INS_SVE_SSRA, INS_SVE_USRA, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, ShiftRightAndInsert, -1, 3, true, {INS_SVE_SRI, INS_SVE_SRI, INS_SVE_SRI, INS_SVE_SRI, INS_SVE_SRI, INS_SVE_SRI, INS_SVE_SRI, INS_SVE_SRI, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, ShiftRightNarrowingLower, -1, 2, true, {INS_SVE_SHRNB, INS_SVE_SHRNB, INS_SVE_SHRNB, INS_SVE_SHRNB, INS_SVE_SHRNB, INS_SVE_SHRNB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, ShiftRightNarrowingUpper, -1, 3, true, {INS_SVE_SHRNT, INS_SVE_SHRNT, INS_SVE_SHRNT, INS_SVE_SHRNT, INS_SVE_SHRNT, INS_SVE_SHRNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SubtractHighNarowingLower, -1, 2, true, {INS_SVE_SUBHNB, INS_SVE_SUBHNB, INS_SVE_SUBHNB, INS_SVE_SUBHNB, INS_SVE_SUBHNB, INS_SVE_SUBHNB, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SubtractHighNarowingUpper, -1, 3, true, {INS_SVE_SUBHNT, INS_SVE_SUBHNT, INS_SVE_SUBHNT, INS_SVE_SUBHNT, INS_SVE_SUBHNT, INS_SVE_SUBHNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SubtractSaturate, -1, 2, true, {INS_SVE_SQSUB, INS_SVE_UQSUB, INS_SVE_SQSUB, INS_SVE_UQSUB, INS_SVE_SQSUB, INS_SVE_UQSUB, INS_SVE_SQSUB, INS_SVE_UQSUB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, SubtractSaturateReversed, -1, 2, true, {INS_SVE_SQSUBR, INS_SVE_UQSUBR, INS_SVE_SQSUBR, INS_SVE_UQSUBR, INS_SVE_SQSUBR, INS_SVE_UQSUBR, INS_SVE_SQSUBR, INS_SVE_UQSUBR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, SubtractWideLower, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SSUBWB, INS_SVE_USUBWB, INS_SVE_SSUBWB, INS_SVE_USUBWB, INS_SVE_SSUBWB, INS_SVE_USUBWB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SubtractWideUpper, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SSUBWT, INS_SVE_USUBWT, INS_SVE_SSUBWT, INS_SVE_USUBWT, INS_SVE_SSUBWT, INS_SVE_USUBWT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SubtractWideningLower, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SSUBLB, INS_SVE_USUBLB, INS_SVE_SSUBLB, INS_SVE_USUBLB, INS_SVE_SSUBLB, INS_SVE_USUBLB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SubtractWideningLowerUpper, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SSUBLBT, INS_invalid, INS_SVE_SSUBLBT, INS_invalid, INS_SVE_SSUBLBT, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SubtractWideningUpper, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SSUBLT, INS_SVE_USUBLT, INS_SVE_SSUBLT, INS_SVE_USUBLT, INS_SVE_SSUBLT, INS_SVE_USUBLT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SubtractWideningUpperLower, -1, 2, true, {INS_invalid, INS_invalid, INS_SVE_SSUBLTB, INS_invalid, INS_SVE_SSUBLTB, INS_invalid, INS_SVE_SSUBLTB, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, SubtractWithBorrowWideningLower, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SBCLB, INS_invalid, INS_SVE_SBCLB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, SubtractWithBorrowWideningUpper, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SBCLT, INS_invalid, INS_SVE_SBCLT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, UpConvertWideningUpper, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTLT} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, VectorTableLookup, -1, 2, true, {INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL, INS_SVE_TBL} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, VectorTableLookupExtension, -1, 3, true, {INS_SVE_TBX, INS_SVE_TBX, INS_SVE_TBX, INS_SVE_TBX, INS_SVE_TBX, INS_SVE_TBX, INS_SVE_TBX, INS_SVE_TBX, INS_SVE_TBX, INS_SVE_TBX} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(Sve2, Xor, -1, 3, true, {INS_SVE_EOR3, INS_SVE_EOR3, INS_SVE_EOR3, INS_SVE_EOR3, INS_SVE_EOR3, INS_SVE_EOR3, INS_SVE_EOR3, INS_SVE_EOR3, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(Sve2, XorRotateRight, -1, 3, true, {INS_SVE_XAR, INS_SVE_XAR, INS_SVE_XAR, INS_SVE_XAR, INS_SVE_XAR, INS_SVE_XAR, INS_SVE_XAR, INS_SVE_XAR, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+
+
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags
+// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// SveBf16
+HARDWARE_INTRINSIC(SveBf16, Bfloat16DotProduct, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_BFDOT, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveBf16, Bfloat16MatrixMultiplyAccumulate, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_BFMMLA, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveBf16, Bfloat16MultiplyAddWideningToSinglePrecisionLower, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_BFMLALB, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveBf16, Bfloat16MultiplyAddWideningToSinglePrecisionUpper, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_BFMLALT, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveBf16, ConditionalExtractAfterLastActiveElement, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, ConditionalExtractLastActiveElement, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, ConditionalSelect, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, ConvertToBFloat16, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveBf16, CreateWhileReadAfterWriteMask, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, CreateWhileWriteAfterReadMask, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, DownConvertNarrowingUpper, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveBf16, DuplicateSelectedScalarToVector, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveBf16, ExtractAfterLast, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, ExtractLast, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, ExtractVector, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, InsertIntoShiftedVector, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, LoadVector, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, LoadVector128AndReplicateToVector, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, LoadVectorFirstFaulting, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, LoadVectorNonFaulting, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, LoadVectorNonTemporal, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, LoadVectorx2, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_MultiReg)
+HARDWARE_INTRINSIC(SveBf16, LoadVectorx3, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_MultiReg)
+HARDWARE_INTRINSIC(SveBf16, LoadVectorx4, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_MultiReg)
+HARDWARE_INTRINSIC(SveBf16, PopCount, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_CNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveBf16, ReverseElement, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, Splice, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, Store, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, StoreNonTemporal, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, Storex2, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, Storex3, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, Storex4, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, TransposeEven, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, TransposeOdd, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, UnzipEven, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, UnzipOdd, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, VectorTableLookup, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveBf16, VectorTableLookupExtension, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveBf16, ZipHigh, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBf16, ZipLow, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+
+
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags
+// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// SveF32mm
+HARDWARE_INTRINSIC(SveF32mm, MatrixMultiplyAccumulate, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMMLA, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+
+
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags
+// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// SveF64mm
+HARDWARE_INTRINSIC(SveF64mm, ConcatenateEvenInt128FromTwoInputs, -1, 2, true, {INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1, INS_SVE_UZP1} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveF64mm, ConcatenateOddInt128FromTwoInputs, -1, 2, true, {INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2, INS_SVE_UZP2} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveF64mm, InterleaveEvenInt128FromTwoInputs, -1, 2, true, {INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1, INS_SVE_TRN1} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveF64mm, InterleaveInt128FromHighHalvesOfTwoInputs, -1, 2, true, {INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2, INS_SVE_ZIP2} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveF64mm, InterleaveInt128FromLowHalvesOfTwoInputs, -1, 2, true, {INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1, INS_SVE_ZIP1} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveF64mm, InterleaveOddInt128FromTwoInputs, -1, 2, true, {INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2, INS_SVE_TRN2} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveF64mm, LoadVector256AndReplicateToVector, -1, 2, true, {INS_SVE_LD1ROB, INS_SVE_LD1ROB, INS_SVE_LD1ROH, INS_SVE_LD1ROH, INS_SVE_LD1ROW, INS_SVE_LD1ROW, INS_SVE_LD1ROD, INS_SVE_LD1ROD, INS_SVE_LD1ROW, INS_SVE_LD1ROD} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveF64mm, MatrixMultiplyAccumulate, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMMLA} HW_Category_SIMD, HW_Flag_NoFlag)
+
+
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags
+// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// SveFp16
+HARDWARE_INTRINSIC(SveFp16, Abs, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, AbsoluteCompareGreaterThan, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, AbsoluteCompareGreaterThanOrEqual, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, AbsoluteCompareLessThan, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, AbsoluteCompareLessThanOrEqual, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, AbsoluteDifference, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, Add, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, AddAcross, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, AddPairwise, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, AddRotateComplex, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, AddSequentialAcross, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, CompareEqual, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, CompareGreaterThan, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, CompareGreaterThanOrEqual, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, CompareLessThan, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, CompareLessThanOrEqual, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, CompareNotEqualTo, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, CompareUnordered, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, ConditionalExtractAfterLastActiveElement, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, ConditionalExtractLastActiveElement, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, ConditionalSelect, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, ConvertToDouble, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVT} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, ConvertToHalf, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveFp16, ConvertToInt16, -1, 1, false, {INS_invalid, INS_invalid, INS_SVE_FCVTZS, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, ConvertToInt32, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTZS, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, ConvertToInt64, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTZS, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, ConvertToSingle, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVT, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, ConvertToUInt16, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTZU, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, ConvertToUInt32, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTZU, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, ConvertToUInt64, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTZU, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, CreateWhileReadAfterWriteMask, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, CreateWhileWriteAfterReadMask, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, Divide, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, DownConvertNarrowingUpper, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, DuplicateSelectedScalarToVector, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveFp16, ExtractAfterLast, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, ExtractLast, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, ExtractVector, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, FloatingPointExponentialAccelerator, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, FusedMultiplyAdd, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveFp16, FusedMultiplyAddNegate, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, FusedMultiplySubtract, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveFp16, FusedMultiplySubtractNegate, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, InsertIntoShiftedVector, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, LoadVector, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, LoadVector128AndReplicateToVector, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, LoadVectorFirstFaulting, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, LoadVectorNonFaulting, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, LoadVectorNonTemporal, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, LoadVectorx2, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_MultiReg)
+HARDWARE_INTRINSIC(SveFp16, LoadVectorx3, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_MultiReg)
+HARDWARE_INTRINSIC(SveFp16, LoadVectorx4, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_MultiReg)
+HARDWARE_INTRINSIC(SveFp16, Log2, -1, 1, false, {INS_invalid, INS_invalid, INS_SVE_FLOGB, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, Max, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, MaxAcross, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, MaxNumber, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, MaxNumberAcross, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, MaxNumberPairwise, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, MaxPairwise, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, Min, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, MinAcross, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, MinNumber, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, MinNumberAcross, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, MinNumberPairwise, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, MinPairwise, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, Multiply, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveFp16, MultiplyAddRotateComplex, -1, 4, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveFp16, MultiplyAddWideningLower, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMLALB, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveFp16, MultiplyAddWideningUpper, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMLALT, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveFp16, MultiplyExtended, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, MultiplySubtractWideningLower, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMLSLB, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveFp16, MultiplySubtractWideningUpper, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FMLSLT, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveFp16, Negate, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, PopCount, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_SVE_CNT, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, ReciprocalEstimate, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, ReciprocalExponent, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, ReciprocalSqrtEstimate, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, ReciprocalSqrtStep, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, ReciprocalStep, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, ReverseElement, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, RoundAwayFromZero, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, RoundToNearest, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, RoundToNegativeInfinity, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, RoundToPositiveInfinity, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, RoundToZero, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, Scale, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, Splice, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, Sqrt, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, Store, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, StoreNonTemporal, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, Storex2, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, Storex3, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, Storex4, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, Subtract, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, SubtractReversed, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, TransposeEven, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, TransposeOdd, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, TrigonometricMultiplyAddCoefficient, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, TrigonometricSelectCoefficient, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, TrigonometricStartingValue, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, UnzipEven, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, UnzipOdd, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, UpConvertWideningUpper, -1, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_FCVTLT, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, VectorTableLookup, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveFp16, VectorTableLookupExtension, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveFp16, ZipHigh, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveFp16, ZipLow, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+
+
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags
+// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// SveI8mm
+HARDWARE_INTRINSIC(SveI8mm, DotProductSignedUnsigned, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_USDOT/INS_SVE_SUDOT,INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveI8mm, DotProductUnsignedSigned, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_USDOT, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(SveI8mm, MatrixMultiplyAccumulate, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SMMLA, INS_SVE_UMMLA, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(SveI8mm, MatrixMultiplyAccumulateUnsignedSigned, -1, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_USMMLA, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
+
+
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags
+// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// SveAes
+HARDWARE_INTRINSIC(SveAes, AesInverseMixColumns, -1, 1, false, {INS_invalid, INS_SVE_AESIMC, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveAes, AesMixColumns, -1, 1, false, {INS_invalid, INS_SVE_AESMC, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveAes, AesSingleRoundDecryption, -1, 2, false, {INS_invalid, INS_SVE_AESD, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveAes, AesSingleRoundEncryption, -1, 2, false, {INS_invalid, INS_SVE_AESE, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveAes, PolynomialMultiplyWideningLower, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_PMULLB, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveAes, PolynomialMultiplyWideningUpper, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_PMULLT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+
+
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags
+// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// SveBitperm
+HARDWARE_INTRINSIC(SveBitperm, GatherLowerBitsFromPositionsSelectedByBitmask, -1, 2, true, {INS_invalid, INS_SVE_BEXT, INS_invalid, INS_SVE_BEXT, INS_invalid, INS_SVE_BEXT, INS_invalid, INS_SVE_BEXT, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBitperm, GroupBitsToRightOrLeftAsSelectedByBitmask, -1, 2, true, {INS_invalid, INS_SVE_BGRP, INS_invalid, INS_SVE_BGRP, INS_invalid, INS_SVE_BGRP, INS_invalid, INS_SVE_BGRP, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveBitperm, ScatterLowerBitsIntoPositionsSelectedByBitmask, -1, 2, true, {INS_invalid, INS_SVE_BDEP, INS_invalid, INS_SVE_BDEP, INS_invalid, INS_SVE_BDEP, INS_invalid, INS_SVE_BDEP, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+
+
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags
+// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// SveSha3
+HARDWARE_INTRINSIC(SveSha3, BitwiseRotateLeftBy1AndXor, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_RAX1, INS_SVE_RAX1, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+
+
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// ISA Function name SIMD size NumArg EncodesExtraTypeArg Instructions Category Flags
+// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+// SveSm4
+HARDWARE_INTRINSIC(SveSm4, Sm4EncryptionAndDecryption, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SM4E, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SveSm4, Sm4KeyUpdates, -1, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_SVE_SM4EKEY, INS_invalid, INS_invalid, INS_invalid, INS_invalid} HW_Category_SIMD, HW_Flag_NoFlag)
+
+
+#endif // FEATURE_HW_INTRINSIC
+
+#undef HARDWARE_INTRINSIC
+
+// clang-format on
+
diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs
new file mode 100644
index 0000000000000..38ac8d3c79109
--- /dev/null
+++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs
@@ -0,0 +1,14058 @@
+// Licensed to the .NET Foundation under one or more agreements.
+// The .NET Foundation licenses this file to you under the MIT license.
+
+using System.Diagnostics.CodeAnalysis;
+using System.Runtime.CompilerServices;
+using System.Runtime.Intrinsics;
+using System.Numerics;
+
+namespace System.Runtime.Intrinsics.Arm
+{
+ ///
+ /// This class provides access to the ARM SVE hardware instructions via intrinsics
+ ///
+ [Intrinsic]
+ [CLSCompliant(false)]
+ public abstract class Sve : AdvSimd
+ {
+ internal Sve() { }
+
+ public static new bool IsSupported { get => IsSupported; }
+
+
+ /// Abs : Absolute value
+
+ ///
+ /// svint8_t svabs[_s8]_m(svint8_t inactive, svbool_t pg, svint8_t op)
+ /// ABS Ztied.B, Pg/M, Zop.B
+ /// MOVPRFX Zresult, Zinactive; ABS Zresult.B, Pg/M, Zop.B
+ /// svint8_t svabs[_s8]_x(svbool_t pg, svint8_t op)
+ /// ABS Ztied.B, Pg/M, Ztied.B
+ /// MOVPRFX Zresult, Zop; ABS Zresult.B, Pg/M, Zop.B
+ /// svint8_t svabs[_s8]_z(svbool_t pg, svint8_t op)
+ /// MOVPRFX Zresult.B, Pg/Z, Zop.B; ABS Zresult.B, Pg/M, Zop.B
+ ///
+ public static unsafe Vector Abs(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint16_t svabs[_s16]_m(svint16_t inactive, svbool_t pg, svint16_t op)
+ /// ABS Ztied.H, Pg/M, Zop.H
+ /// MOVPRFX Zresult, Zinactive; ABS Zresult.H, Pg/M, Zop.H
+ /// svint16_t svabs[_s16]_x(svbool_t pg, svint16_t op)
+ /// ABS Ztied.H, Pg/M, Ztied.H
+ /// MOVPRFX Zresult, Zop; ABS Zresult.H, Pg/M, Zop.H
+ /// svint16_t svabs[_s16]_z(svbool_t pg, svint16_t op)
+ /// MOVPRFX Zresult.H, Pg/Z, Zop.H; ABS Zresult.H, Pg/M, Zop.H
+ ///
+ public static unsafe Vector Abs(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint32_t svabs[_s32]_m(svint32_t inactive, svbool_t pg, svint32_t op)
+ /// ABS Ztied.S, Pg/M, Zop.S
+ /// MOVPRFX Zresult, Zinactive; ABS Zresult.S, Pg/M, Zop.S
+ /// svint32_t svabs[_s32]_x(svbool_t pg, svint32_t op)
+ /// ABS Ztied.S, Pg/M, Ztied.S
+ /// MOVPRFX Zresult, Zop; ABS Zresult.S, Pg/M, Zop.S
+ /// svint32_t svabs[_s32]_z(svbool_t pg, svint32_t op)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop.S; ABS Zresult.S, Pg/M, Zop.S
+ ///
+ public static unsafe Vector Abs(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint64_t svabs[_s64]_m(svint64_t inactive, svbool_t pg, svint64_t op)
+ /// ABS Ztied.D, Pg/M, Zop.D
+ /// MOVPRFX Zresult, Zinactive; ABS Zresult.D, Pg/M, Zop.D
+ /// svint64_t svabs[_s64]_x(svbool_t pg, svint64_t op)
+ /// ABS Ztied.D, Pg/M, Ztied.D
+ /// MOVPRFX Zresult, Zop; ABS Zresult.D, Pg/M, Zop.D
+ /// svint64_t svabs[_s64]_z(svbool_t pg, svint64_t op)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop.D; ABS Zresult.D, Pg/M, Zop.D
+ ///
+ public static unsafe Vector Abs(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svfloat32_t svabs[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op)
+ /// FABS Ztied.S, Pg/M, Zop.S
+ /// MOVPRFX Zresult, Zinactive; FABS Zresult.S, Pg/M, Zop.S
+ /// svfloat32_t svabs[_f32]_x(svbool_t pg, svfloat32_t op)
+ /// FABS Ztied.S, Pg/M, Ztied.S
+ /// MOVPRFX Zresult, Zop; FABS Zresult.S, Pg/M, Zop.S
+ /// svfloat32_t svabs[_f32]_z(svbool_t pg, svfloat32_t op)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop.S; FABS Zresult.S, Pg/M, Zop.S
+ ///
+ public static unsafe Vector Abs(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svfloat64_t svabs[_f64]_m(svfloat64_t inactive, svbool_t pg, svfloat64_t op)
+ /// FABS Ztied.D, Pg/M, Zop.D
+ /// MOVPRFX Zresult, Zinactive; FABS Zresult.D, Pg/M, Zop.D
+ /// svfloat64_t svabs[_f64]_x(svbool_t pg, svfloat64_t op)
+ /// FABS Ztied.D, Pg/M, Ztied.D
+ /// MOVPRFX Zresult, Zop; FABS Zresult.D, Pg/M, Zop.D
+ /// svfloat64_t svabs[_f64]_z(svbool_t pg, svfloat64_t op)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop.D; FABS Zresult.D, Pg/M, Zop.D
+ ///
+ public static unsafe Vector Abs(Vector value) { throw new PlatformNotSupportedException(); }
+
+
+ /// AbsoluteCompareGreaterThan : Absolute compare greater than
+
+ ///
+ /// svbool_t svacgt[_f32](svbool_t pg, svfloat32_t op1, svfloat32_t op2)
+ /// FACGT Presult.S, Pg/Z, Zop1.S, Zop2.S
+ ///
+ public static unsafe Vector AbsoluteCompareGreaterThan(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svbool_t svacgt[_f64](svbool_t pg, svfloat64_t op1, svfloat64_t op2)
+ /// FACGT Presult.D, Pg/Z, Zop1.D, Zop2.D
+ ///
+ public static unsafe Vector AbsoluteCompareGreaterThan(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+
+ /// AbsoluteCompareGreaterThanOrEqual : Absolute compare greater than or equal to
+
+ ///
+ /// svbool_t svacge[_f32](svbool_t pg, svfloat32_t op1, svfloat32_t op2)
+ /// FACGE Presult.S, Pg/Z, Zop1.S, Zop2.S
+ ///
+ public static unsafe Vector AbsoluteCompareGreaterThanOrEqual(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svbool_t svacge[_f64](svbool_t pg, svfloat64_t op1, svfloat64_t op2)
+ /// FACGE Presult.D, Pg/Z, Zop1.D, Zop2.D
+ ///
+ public static unsafe Vector AbsoluteCompareGreaterThanOrEqual(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+
+ /// AbsoluteCompareLessThan : Absolute compare less than
+
+ ///
+ /// svbool_t svaclt[_f32](svbool_t pg, svfloat32_t op1, svfloat32_t op2)
+ /// FACGT Presult.S, Pg/Z, Zop2.S, Zop1.S
+ ///
+ public static unsafe Vector AbsoluteCompareLessThan(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svbool_t svaclt[_f64](svbool_t pg, svfloat64_t op1, svfloat64_t op2)
+ /// FACGT Presult.D, Pg/Z, Zop2.D, Zop1.D
+ ///
+ public static unsafe Vector AbsoluteCompareLessThan(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+
+ /// AbsoluteCompareLessThanOrEqual : Absolute compare less than or equal to
+
+ ///
+ /// svbool_t svacle[_f32](svbool_t pg, svfloat32_t op1, svfloat32_t op2)
+ /// FACGE Presult.S, Pg/Z, Zop2.S, Zop1.S
+ ///
+ public static unsafe Vector AbsoluteCompareLessThanOrEqual(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svbool_t svacle[_f64](svbool_t pg, svfloat64_t op1, svfloat64_t op2)
+ /// FACGE Presult.D, Pg/Z, Zop2.D, Zop1.D
+ ///
+ public static unsafe Vector AbsoluteCompareLessThanOrEqual(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+
+ /// AbsoluteDifference : Absolute difference
+
+ ///
+ /// svint8_t svabd[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2)
+ /// SABD Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// MOVPRFX Zresult, Zop1; SABD Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// svint8_t svabd[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2)
+ /// SABD Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// SABD Ztied2.B, Pg/M, Ztied2.B, Zop1.B
+ /// MOVPRFX Zresult, Zop1; SABD Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// svint8_t svabd[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2)
+ /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; SABD Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; SABD Zresult.B, Pg/M, Zresult.B, Zop1.B
+ ///
+ public static unsafe Vector AbsoluteDifference(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint16_t svabd[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2)
+ /// SABD Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// MOVPRFX Zresult, Zop1; SABD Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// svint16_t svabd[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2)
+ /// SABD Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// SABD Ztied2.H, Pg/M, Ztied2.H, Zop1.H
+ /// MOVPRFX Zresult, Zop1; SABD Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// svint16_t svabd[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2)
+ /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; SABD Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; SABD Zresult.H, Pg/M, Zresult.H, Zop1.H
+ ///
+ public static unsafe Vector AbsoluteDifference(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint32_t svabd[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2)
+ /// SABD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// MOVPRFX Zresult, Zop1; SABD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svint32_t svabd[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2)
+ /// SABD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// SABD Ztied2.S, Pg/M, Ztied2.S, Zop1.S
+ /// MOVPRFX Zresult, Zop1; SABD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svint32_t svabd[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; SABD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; SABD Zresult.S, Pg/M, Zresult.S, Zop1.S
+ ///
+ public static unsafe Vector AbsoluteDifference(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint64_t svabd[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2)
+ /// SABD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// MOVPRFX Zresult, Zop1; SABD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svint64_t svabd[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2)
+ /// SABD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// SABD Ztied2.D, Pg/M, Ztied2.D, Zop1.D
+ /// MOVPRFX Zresult, Zop1; SABD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svint64_t svabd[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; SABD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; SABD Zresult.D, Pg/M, Zresult.D, Zop1.D
+ ///
+ public static unsafe Vector AbsoluteDifference(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint8_t svabd[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
+ /// UABD Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// MOVPRFX Zresult, Zop1; UABD Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// svuint8_t svabd[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
+ /// UABD Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// UABD Ztied2.B, Pg/M, Ztied2.B, Zop1.B
+ /// MOVPRFX Zresult, Zop1; UABD Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// svuint8_t svabd[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
+ /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; UABD Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; UABD Zresult.B, Pg/M, Zresult.B, Zop1.B
+ ///
+ public static unsafe Vector AbsoluteDifference(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint16_t svabd[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
+ /// UABD Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// MOVPRFX Zresult, Zop1; UABD Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// svuint16_t svabd[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
+ /// UABD Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// UABD Ztied2.H, Pg/M, Ztied2.H, Zop1.H
+ /// MOVPRFX Zresult, Zop1; UABD Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// svuint16_t svabd[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
+ /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; UABD Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; UABD Zresult.H, Pg/M, Zresult.H, Zop1.H
+ ///
+ public static unsafe Vector AbsoluteDifference(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint32_t svabd[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
+ /// UABD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// MOVPRFX Zresult, Zop1; UABD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svuint32_t svabd[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
+ /// UABD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// UABD Ztied2.S, Pg/M, Ztied2.S, Zop1.S
+ /// MOVPRFX Zresult, Zop1; UABD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svuint32_t svabd[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; UABD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; UABD Zresult.S, Pg/M, Zresult.S, Zop1.S
+ ///
+ public static unsafe Vector AbsoluteDifference(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint64_t svabd[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
+ /// UABD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// MOVPRFX Zresult, Zop1; UABD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svuint64_t svabd[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
+ /// UABD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// UABD Ztied2.D, Pg/M, Ztied2.D, Zop1.D
+ /// MOVPRFX Zresult, Zop1; UABD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svuint64_t svabd[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; UABD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; UABD Zresult.D, Pg/M, Zresult.D, Zop1.D
+ ///
+ public static unsafe Vector AbsoluteDifference(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svfloat32_t svabd[_f32]_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
+ /// FABD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// MOVPRFX Zresult, Zop1; FABD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svfloat32_t svabd[_f32]_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
+ /// FABD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// FABD Ztied2.S, Pg/M, Ztied2.S, Zop1.S
+ /// MOVPRFX Zresult, Zop1; FABD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svfloat32_t svabd[_f32]_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; FABD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; FABD Zresult.S, Pg/M, Zresult.S, Zop1.S
+ ///
+ public static unsafe Vector AbsoluteDifference(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svfloat64_t svabd[_f64]_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
+ /// FABD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// MOVPRFX Zresult, Zop1; FABD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svfloat64_t svabd[_f64]_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
+ /// FABD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// FABD Ztied2.D, Pg/M, Ztied2.D, Zop1.D
+ /// MOVPRFX Zresult, Zop1; FABD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svfloat64_t svabd[_f64]_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; FABD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; FABD Zresult.D, Pg/M, Zresult.D, Zop1.D
+ ///
+ public static unsafe Vector AbsoluteDifference(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+
+ /// Add : Add
+
+ ///
+ /// svint8_t svadd[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2)
+ /// ADD Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// MOVPRFX Zresult, Zop1; ADD Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// svint8_t svadd[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2)
+ /// ADD Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// ADD Ztied2.B, Pg/M, Ztied2.B, Zop1.B
+ /// ADD Zresult.B, Zop1.B, Zop2.B
+ /// svint8_t svadd[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2)
+ /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; ADD Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; ADD Zresult.B, Pg/M, Zresult.B, Zop1.B
+ ///
+ public static unsafe Vector Add(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint16_t svadd[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2)
+ /// ADD Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// MOVPRFX Zresult, Zop1; ADD Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// svint16_t svadd[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2)
+ /// ADD Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// ADD Ztied2.H, Pg/M, Ztied2.H, Zop1.H
+ /// ADD Zresult.H, Zop1.H, Zop2.H
+ /// svint16_t svadd[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2)
+ /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; ADD Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; ADD Zresult.H, Pg/M, Zresult.H, Zop1.H
+ ///
+ public static unsafe Vector Add(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint32_t svadd[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2)
+ /// ADD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// MOVPRFX Zresult, Zop1; ADD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svint32_t svadd[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2)
+ /// ADD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// ADD Ztied2.S, Pg/M, Ztied2.S, Zop1.S
+ /// ADD Zresult.S, Zop1.S, Zop2.S
+ /// svint32_t svadd[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; ADD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; ADD Zresult.S, Pg/M, Zresult.S, Zop1.S
+ ///
+ public static unsafe Vector Add(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint64_t svadd[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2)
+ /// ADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// MOVPRFX Zresult, Zop1; ADD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svint64_t svadd[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2)
+ /// ADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// ADD Ztied2.D, Pg/M, Ztied2.D, Zop1.D
+ /// ADD Zresult.D, Zop1.D, Zop2.D
+ /// svint64_t svadd[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; ADD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; ADD Zresult.D, Pg/M, Zresult.D, Zop1.D
+ ///
+ public static unsafe Vector Add(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint8_t svadd[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
+ /// ADD Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// MOVPRFX Zresult, Zop1; ADD Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// svuint8_t svadd[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
+ /// ADD Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// ADD Ztied2.B, Pg/M, Ztied2.B, Zop1.B
+ /// ADD Zresult.B, Zop1.B, Zop2.B
+ /// svuint8_t svadd[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
+ /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; ADD Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; ADD Zresult.B, Pg/M, Zresult.B, Zop1.B
+ ///
+ public static unsafe Vector Add(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint16_t svadd[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
+ /// ADD Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// MOVPRFX Zresult, Zop1; ADD Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// svuint16_t svadd[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
+ /// ADD Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// ADD Ztied2.H, Pg/M, Ztied2.H, Zop1.H
+ /// ADD Zresult.H, Zop1.H, Zop2.H
+ /// svuint16_t svadd[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
+ /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; ADD Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; ADD Zresult.H, Pg/M, Zresult.H, Zop1.H
+ ///
+ public static unsafe Vector Add(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint32_t svadd[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
+ /// ADD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// MOVPRFX Zresult, Zop1; ADD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svuint32_t svadd[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
+ /// ADD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// ADD Ztied2.S, Pg/M, Ztied2.S, Zop1.S
+ /// ADD Zresult.S, Zop1.S, Zop2.S
+ /// svuint32_t svadd[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; ADD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; ADD Zresult.S, Pg/M, Zresult.S, Zop1.S
+ ///
+ public static unsafe Vector Add(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint64_t svadd[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
+ /// ADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// MOVPRFX Zresult, Zop1; ADD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svuint64_t svadd[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
+ /// ADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// ADD Ztied2.D, Pg/M, Ztied2.D, Zop1.D
+ /// ADD Zresult.D, Zop1.D, Zop2.D
+ /// svuint64_t svadd[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; ADD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; ADD Zresult.D, Pg/M, Zresult.D, Zop1.D
+ ///
+ public static unsafe Vector Add(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svfloat32_t svadd[_f32]_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
+ /// FADD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// MOVPRFX Zresult, Zop1; FADD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svfloat32_t svadd[_f32]_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
+ /// FADD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// FADD Ztied2.S, Pg/M, Ztied2.S, Zop1.S
+ /// FADD Zresult.S, Zop1.S, Zop2.S
+ /// MOVPRFX Zresult, Zop1; FADD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svfloat32_t svadd[_f32]_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; FADD Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; FADD Zresult.S, Pg/M, Zresult.S, Zop1.S
+ ///
+ public static unsafe Vector Add(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svfloat64_t svadd[_f64]_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
+ /// FADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// MOVPRFX Zresult, Zop1; FADD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svfloat64_t svadd[_f64]_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
+ /// FADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// FADD Ztied2.D, Pg/M, Ztied2.D, Zop1.D
+ /// FADD Zresult.D, Zop1.D, Zop2.D
+ /// MOVPRFX Zresult, Zop1; FADD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svfloat64_t svadd[_f64]_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; FADD Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; FADD Zresult.D, Pg/M, Zresult.D, Zop1.D
+ ///
+ public static unsafe Vector Add(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+
+ /// AddAcross : Add reduction
+
+ ///
+ /// int64_t svaddv[_s8](svbool_t pg, svint8_t op)
+ /// SADDV Dresult, Pg, Zop.B
+ ///
+ public static unsafe long AddAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// int64_t svaddv[_s16](svbool_t pg, svint16_t op)
+ /// SADDV Dresult, Pg, Zop.H
+ ///
+ public static unsafe long AddAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// int64_t svaddv[_s32](svbool_t pg, svint32_t op)
+ /// SADDV Dresult, Pg, Zop.S
+ ///
+ public static unsafe long AddAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// int64_t svaddv[_s64](svbool_t pg, svint64_t op)
+ /// UADDV Dresult, Pg, Zop.D
+ ///
+ public static unsafe long AddAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// uint64_t svaddv[_u8](svbool_t pg, svuint8_t op)
+ /// UADDV Dresult, Pg, Zop.B
+ ///
+ public static unsafe ulong AddAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// uint64_t svaddv[_u16](svbool_t pg, svuint16_t op)
+ /// UADDV Dresult, Pg, Zop.H
+ ///
+ public static unsafe ulong AddAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// uint64_t svaddv[_u32](svbool_t pg, svuint32_t op)
+ /// UADDV Dresult, Pg, Zop.S
+ ///
+ public static unsafe ulong AddAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// uint64_t svaddv[_u64](svbool_t pg, svuint64_t op)
+ /// UADDV Dresult, Pg, Zop.D
+ ///
+ public static unsafe ulong AddAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// float32_t svaddv[_f32](svbool_t pg, svfloat32_t op)
+ /// FADDV Sresult, Pg, Zop.S
+ ///
+ public static unsafe float AddAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// float64_t svaddv[_f64](svbool_t pg, svfloat64_t op)
+ /// FADDV Dresult, Pg, Zop.D
+ ///
+ public static unsafe double AddAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+
+ /// AddRotateComplex : Complex add with rotate
+
+ ///
+ /// svfloat32_t svcadd[_f32]_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, uint64_t imm_rotation)
+ /// FCADD Ztied1.S, Pg/M, Ztied1.S, Zop2.S, #imm_rotation
+ /// MOVPRFX Zresult, Zop1; FCADD Zresult.S, Pg/M, Zresult.S, Zop2.S, #imm_rotation
+ /// svfloat32_t svcadd[_f32]_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, uint64_t imm_rotation)
+ /// FCADD Ztied1.S, Pg/M, Ztied1.S, Zop2.S, #imm_rotation
+ /// MOVPRFX Zresult, Zop1; FCADD Zresult.S, Pg/M, Zresult.S, Zop2.S, #imm_rotation
+ /// svfloat32_t svcadd[_f32]_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, uint64_t imm_rotation)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; FCADD Zresult.S, Pg/M, Zresult.S, Zop2.S, #imm_rotation
+ ///
+ public static unsafe Vector AddRotateComplex(Vector op1, Vector op2, ulong imm_rotation) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svfloat64_t svcadd[_f64]_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, uint64_t imm_rotation)
+ /// FCADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D, #imm_rotation
+ /// MOVPRFX Zresult, Zop1; FCADD Zresult.D, Pg/M, Zresult.D, Zop2.D, #imm_rotation
+ /// svfloat64_t svcadd[_f64]_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, uint64_t imm_rotation)
+ /// FCADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D, #imm_rotation
+ /// MOVPRFX Zresult, Zop1; FCADD Zresult.D, Pg/M, Zresult.D, Zop2.D, #imm_rotation
+ /// svfloat64_t svcadd[_f64]_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, uint64_t imm_rotation)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; FCADD Zresult.D, Pg/M, Zresult.D, Zop2.D, #imm_rotation
+ ///
+ public static unsafe Vector AddRotateComplex(Vector op1, Vector op2, ulong imm_rotation) { throw new PlatformNotSupportedException(); }
+
+
+ /// AddSaturate : Saturating add
+
+ ///
+ /// svint8_t svqadd[_s8](svint8_t op1, svint8_t op2)
+ /// SQADD Zresult.B, Zop1.B, Zop2.B
+ ///
+ public static unsafe Vector AddSaturate(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint16_t svqadd[_s16](svint16_t op1, svint16_t op2)
+ /// SQADD Zresult.H, Zop1.H, Zop2.H
+ ///
+ public static unsafe Vector AddSaturate(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint32_t svqadd[_s32](svint32_t op1, svint32_t op2)
+ /// SQADD Zresult.S, Zop1.S, Zop2.S
+ ///
+ public static unsafe Vector AddSaturate(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint64_t svqadd[_s64](svint64_t op1, svint64_t op2)
+ /// SQADD Zresult.D, Zop1.D, Zop2.D
+ ///
+ public static unsafe Vector AddSaturate(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint8_t svqadd[_u8](svuint8_t op1, svuint8_t op2)
+ /// UQADD Zresult.B, Zop1.B, Zop2.B
+ ///
+ public static unsafe Vector AddSaturate(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint16_t svqadd[_u16](svuint16_t op1, svuint16_t op2)
+ /// UQADD Zresult.H, Zop1.H, Zop2.H
+ ///
+ public static unsafe Vector AddSaturate(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint32_t svqadd[_u32](svuint32_t op1, svuint32_t op2)
+ /// UQADD Zresult.S, Zop1.S, Zop2.S
+ ///
+ public static unsafe Vector AddSaturate(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint64_t svqadd[_u64](svuint64_t op1, svuint64_t op2)
+ /// UQADD Zresult.D, Zop1.D, Zop2.D
+ ///
+ public static unsafe Vector AddSaturate(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+
+ /// AddSequentialAcross : Add reduction (strictly-ordered)
+
+ ///
+ /// float32_t svadda[_f32](svbool_t pg, float32_t initial, svfloat32_t op)
+ /// FADDA Stied, Pg, Stied, Zop.S
+ ///
+ public static unsafe float AddSequentialAcross(float initial, Vector op) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// float64_t svadda[_f64](svbool_t pg, float64_t initial, svfloat64_t op)
+ /// FADDA Dtied, Pg, Dtied, Zop.D
+ ///
+ public static unsafe double AddSequentialAcross(double initial, Vector op) { throw new PlatformNotSupportedException(); }
+
+
+ /// And : Bitwise AND
+
+ ///
+ /// svint8_t svand[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2)
+ /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// MOVPRFX Zresult, Zop1; AND Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// svint8_t svand[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2)
+ /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// AND Ztied2.B, Pg/M, Ztied2.B, Zop1.B
+ /// AND Zresult.D, Zop1.D, Zop2.D
+ /// svint8_t svand[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2)
+ /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; AND Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; AND Zresult.B, Pg/M, Zresult.B, Zop1.B
+ /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint16_t svand[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2)
+ /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// MOVPRFX Zresult, Zop1; AND Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// svint16_t svand[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2)
+ /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// AND Ztied2.H, Pg/M, Ztied2.H, Zop1.H
+ /// AND Zresult.D, Zop1.D, Zop2.D
+ /// svint16_t svand[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2)
+ /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; AND Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; AND Zresult.H, Pg/M, Zresult.H, Zop1.H
+ /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint32_t svand[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2)
+ /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// MOVPRFX Zresult, Zop1; AND Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svint32_t svand[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2)
+ /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// AND Ztied2.S, Pg/M, Ztied2.S, Zop1.S
+ /// AND Zresult.D, Zop1.D, Zop2.D
+ /// svint32_t svand[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; AND Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; AND Zresult.S, Pg/M, Zresult.S, Zop1.S
+ /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint64_t svand[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2)
+ /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// MOVPRFX Zresult, Zop1; AND Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svint64_t svand[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2)
+ /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// AND Ztied2.D, Pg/M, Ztied2.D, Zop1.D
+ /// AND Zresult.D, Zop1.D, Zop2.D
+ /// svint64_t svand[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; AND Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; AND Zresult.D, Pg/M, Zresult.D, Zop1.D
+ /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint8_t svand[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
+ /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// MOVPRFX Zresult, Zop1; AND Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// svuint8_t svand[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
+ /// AND Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// AND Ztied2.B, Pg/M, Ztied2.B, Zop1.B
+ /// AND Zresult.D, Zop1.D, Zop2.D
+ /// svuint8_t svand[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
+ /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; AND Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// MOVPRFX Zresult.B, Pg/Z, Zop2.B; AND Zresult.B, Pg/M, Zresult.B, Zop1.B
+ /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint16_t svand[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
+ /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// MOVPRFX Zresult, Zop1; AND Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// svuint16_t svand[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
+ /// AND Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// AND Ztied2.H, Pg/M, Ztied2.H, Zop1.H
+ /// AND Zresult.D, Zop1.D, Zop2.D
+ /// svuint16_t svand[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
+ /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; AND Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// MOVPRFX Zresult.H, Pg/Z, Zop2.H; AND Zresult.H, Pg/M, Zresult.H, Zop1.H
+ /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint32_t svand[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
+ /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// MOVPRFX Zresult, Zop1; AND Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svuint32_t svand[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
+ /// AND Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// AND Ztied2.S, Pg/M, Ztied2.S, Zop1.S
+ /// AND Zresult.D, Zop1.D, Zop2.D
+ /// svuint32_t svand[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; AND Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// MOVPRFX Zresult.S, Pg/Z, Zop2.S; AND Zresult.S, Pg/M, Zresult.S, Zop1.S
+ /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint64_t svand[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
+ /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// MOVPRFX Zresult, Zop1; AND Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svuint64_t svand[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
+ /// AND Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// AND Ztied2.D, Pg/M, Ztied2.D, Zop1.D
+ /// AND Zresult.D, Zop1.D, Zop2.D
+ /// svuint64_t svand[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; AND Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// MOVPRFX Zresult.D, Pg/Z, Zop2.D; AND Zresult.D, Pg/M, Zresult.D, Zop1.D
+ /// svbool_t svand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// AND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector And(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+
+ /// AndAcross : Bitwise AND reduction to scalar
+
+ ///
+ /// int8_t svandv[_s8](svbool_t pg, svint8_t op)
+ /// ANDV Bresult, Pg, Zop.B
+ ///
+ public static unsafe sbyte AndAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// int16_t svandv[_s16](svbool_t pg, svint16_t op)
+ /// ANDV Hresult, Pg, Zop.H
+ ///
+ public static unsafe short AndAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// int32_t svandv[_s32](svbool_t pg, svint32_t op)
+ /// ANDV Sresult, Pg, Zop.S
+ ///
+ public static unsafe int AndAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// int64_t svandv[_s64](svbool_t pg, svint64_t op)
+ /// ANDV Dresult, Pg, Zop.D
+ ///
+ public static unsafe long AndAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// uint8_t svandv[_u8](svbool_t pg, svuint8_t op)
+ /// ANDV Bresult, Pg, Zop.B
+ ///
+ public static unsafe byte AndAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// uint16_t svandv[_u16](svbool_t pg, svuint16_t op)
+ /// ANDV Hresult, Pg, Zop.H
+ ///
+ public static unsafe ushort AndAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// uint32_t svandv[_u32](svbool_t pg, svuint32_t op)
+ /// ANDV Sresult, Pg, Zop.S
+ ///
+ public static unsafe uint AndAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// uint64_t svandv[_u64](svbool_t pg, svuint64_t op)
+ /// ANDV Dresult, Pg, Zop.D
+ ///
+ public static unsafe ulong AndAcross(Vector value) { throw new PlatformNotSupportedException(); }
+
+
+ /// AndNot : Bitwise NAND
+
+ ///
+ /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+
+ /// BitwiseClear : Bitwise clear
+
+ ///
+ /// svint8_t svbic[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2)
+ /// BIC Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// MOVPRFX Zresult, Zop1; BIC Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// svint8_t svbic[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2)
+ /// BIC Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// BIC Zresult.D, Zop1.D, Zop2.D
+ /// svint8_t svbic[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2)
+ /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; BIC Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector BitwiseClear(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint16_t svbic[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2)
+ /// BIC Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// MOVPRFX Zresult, Zop1; BIC Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// svint16_t svbic[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2)
+ /// BIC Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// BIC Zresult.D, Zop1.D, Zop2.D
+ /// svint16_t svbic[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2)
+ /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; BIC Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector BitwiseClear(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint32_t svbic[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2)
+ /// BIC Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// MOVPRFX Zresult, Zop1; BIC Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svint32_t svbic[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2)
+ /// BIC Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// BIC Zresult.D, Zop1.D, Zop2.D
+ /// svint32_t svbic[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; BIC Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector BitwiseClear(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint64_t svbic[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2)
+ /// BIC Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// MOVPRFX Zresult, Zop1; BIC Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svint64_t svbic[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2)
+ /// BIC Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// BIC Zresult.D, Zop1.D, Zop2.D
+ /// svint64_t svbic[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; BIC Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector BitwiseClear(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint8_t svbic[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
+ /// BIC Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// MOVPRFX Zresult, Zop1; BIC Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// svuint8_t svbic[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
+ /// BIC Ztied1.B, Pg/M, Ztied1.B, Zop2.B
+ /// BIC Zresult.D, Zop1.D, Zop2.D
+ /// svuint8_t svbic[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
+ /// MOVPRFX Zresult.B, Pg/Z, Zop1.B; BIC Zresult.B, Pg/M, Zresult.B, Zop2.B
+ /// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector BitwiseClear(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint16_t svbic[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
+ /// BIC Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// MOVPRFX Zresult, Zop1; BIC Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// svuint16_t svbic[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
+ /// BIC Ztied1.H, Pg/M, Ztied1.H, Zop2.H
+ /// BIC Zresult.D, Zop1.D, Zop2.D
+ /// svuint16_t svbic[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
+ /// MOVPRFX Zresult.H, Pg/Z, Zop1.H; BIC Zresult.H, Pg/M, Zresult.H, Zop2.H
+ /// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector BitwiseClear(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint32_t svbic[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
+ /// BIC Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// MOVPRFX Zresult, Zop1; BIC Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svuint32_t svbic[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
+ /// BIC Ztied1.S, Pg/M, Ztied1.S, Zop2.S
+ /// BIC Zresult.D, Zop1.D, Zop2.D
+ /// svuint32_t svbic[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop1.S; BIC Zresult.S, Pg/M, Zresult.S, Zop2.S
+ /// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector BitwiseClear(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint64_t svbic[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
+ /// BIC Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// MOVPRFX Zresult, Zop1; BIC Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svuint64_t svbic[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
+ /// BIC Ztied1.D, Pg/M, Ztied1.D, Zop2.D
+ /// BIC Zresult.D, Zop1.D, Zop2.D
+ /// svuint64_t svbic[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop1.D; BIC Zresult.D, Pg/M, Zresult.D, Zop2.D
+ /// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static unsafe Vector BitwiseClear(Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
+
+ /// Cnot : Logically invert boolean condition
+
+ ///
+ /// svint8_t svcnot[_s8]_m(svint8_t inactive, svbool_t pg, svint8_t op)
+ /// CNOT Ztied.B, Pg/M, Zop.B
+ /// MOVPRFX Zresult, Zinactive; CNOT Zresult.B, Pg/M, Zop.B
+ /// svint8_t svcnot[_s8]_x(svbool_t pg, svint8_t op)
+ /// CNOT Ztied.B, Pg/M, Ztied.B
+ /// MOVPRFX Zresult, Zop; CNOT Zresult.B, Pg/M, Zop.B
+ /// svint8_t svcnot[_s8]_z(svbool_t pg, svint8_t op)
+ /// MOVPRFX Zresult.B, Pg/Z, Zop.B; CNOT Zresult.B, Pg/M, Zop.B
+ ///
+ public static unsafe Vector Cnot(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint16_t svcnot[_s16]_m(svint16_t inactive, svbool_t pg, svint16_t op)
+ /// CNOT Ztied.H, Pg/M, Zop.H
+ /// MOVPRFX Zresult, Zinactive; CNOT Zresult.H, Pg/M, Zop.H
+ /// svint16_t svcnot[_s16]_x(svbool_t pg, svint16_t op)
+ /// CNOT Ztied.H, Pg/M, Ztied.H
+ /// MOVPRFX Zresult, Zop; CNOT Zresult.H, Pg/M, Zop.H
+ /// svint16_t svcnot[_s16]_z(svbool_t pg, svint16_t op)
+ /// MOVPRFX Zresult.H, Pg/Z, Zop.H; CNOT Zresult.H, Pg/M, Zop.H
+ ///
+ public static unsafe Vector Cnot(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint32_t svcnot[_s32]_m(svint32_t inactive, svbool_t pg, svint32_t op)
+ /// CNOT Ztied.S, Pg/M, Zop.S
+ /// MOVPRFX Zresult, Zinactive; CNOT Zresult.S, Pg/M, Zop.S
+ /// svint32_t svcnot[_s32]_x(svbool_t pg, svint32_t op)
+ /// CNOT Ztied.S, Pg/M, Ztied.S
+ /// MOVPRFX Zresult, Zop; CNOT Zresult.S, Pg/M, Zop.S
+ /// svint32_t svcnot[_s32]_z(svbool_t pg, svint32_t op)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop.S; CNOT Zresult.S, Pg/M, Zop.S
+ ///
+ public static unsafe Vector Cnot(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint64_t svcnot[_s64]_m(svint64_t inactive, svbool_t pg, svint64_t op)
+ /// CNOT Ztied.D, Pg/M, Zop.D
+ /// MOVPRFX Zresult, Zinactive; CNOT Zresult.D, Pg/M, Zop.D
+ /// svint64_t svcnot[_s64]_x(svbool_t pg, svint64_t op)
+ /// CNOT Ztied.D, Pg/M, Ztied.D
+ /// MOVPRFX Zresult, Zop; CNOT Zresult.D, Pg/M, Zop.D
+ /// svint64_t svcnot[_s64]_z(svbool_t pg, svint64_t op)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop.D; CNOT Zresult.D, Pg/M, Zop.D
+ ///
+ public static unsafe Vector Cnot(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint8_t svcnot[_u8]_m(svuint8_t inactive, svbool_t pg, svuint8_t op)
+ /// CNOT Ztied.B, Pg/M, Zop.B
+ /// MOVPRFX Zresult, Zinactive; CNOT Zresult.B, Pg/M, Zop.B
+ /// svuint8_t svcnot[_u8]_x(svbool_t pg, svuint8_t op)
+ /// CNOT Ztied.B, Pg/M, Ztied.B
+ /// MOVPRFX Zresult, Zop; CNOT Zresult.B, Pg/M, Zop.B
+ /// svuint8_t svcnot[_u8]_z(svbool_t pg, svuint8_t op)
+ /// MOVPRFX Zresult.B, Pg/Z, Zop.B; CNOT Zresult.B, Pg/M, Zop.B
+ ///
+ public static unsafe Vector Cnot(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint16_t svcnot[_u16]_m(svuint16_t inactive, svbool_t pg, svuint16_t op)
+ /// CNOT Ztied.H, Pg/M, Zop.H
+ /// MOVPRFX Zresult, Zinactive; CNOT Zresult.H, Pg/M, Zop.H
+ /// svuint16_t svcnot[_u16]_x(svbool_t pg, svuint16_t op)
+ /// CNOT Ztied.H, Pg/M, Ztied.H
+ /// MOVPRFX Zresult, Zop; CNOT Zresult.H, Pg/M, Zop.H
+ /// svuint16_t svcnot[_u16]_z(svbool_t pg, svuint16_t op)
+ /// MOVPRFX Zresult.H, Pg/Z, Zop.H; CNOT Zresult.H, Pg/M, Zop.H
+ ///
+ public static unsafe Vector Cnot(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint32_t svcnot[_u32]_m(svuint32_t inactive, svbool_t pg, svuint32_t op)
+ /// CNOT Ztied.S, Pg/M, Zop.S
+ /// MOVPRFX Zresult, Zinactive; CNOT Zresult.S, Pg/M, Zop.S
+ /// svuint32_t svcnot[_u32]_x(svbool_t pg, svuint32_t op)
+ /// CNOT Ztied.S, Pg/M, Ztied.S
+ /// MOVPRFX Zresult, Zop; CNOT Zresult.S, Pg/M, Zop.S
+ /// svuint32_t svcnot[_u32]_z(svbool_t pg, svuint32_t op)
+ /// MOVPRFX Zresult.S, Pg/Z, Zop.S; CNOT Zresult.S, Pg/M, Zop.S
+ ///
+ public static unsafe Vector Cnot(Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint64_t svcnot[_u64]_m(svuint64_t inactive, svbool_t pg, svuint64_t op)
+ /// CNOT Ztied.D, Pg/M, Zop.D
+ /// MOVPRFX Zresult, Zinactive; CNOT Zresult.D, Pg/M, Zop.D
+ /// svuint64_t svcnot[_u64]_x(svbool_t pg, svuint64_t op)
+ /// CNOT Ztied.D, Pg/M, Ztied.D
+ /// MOVPRFX Zresult, Zop; CNOT Zresult.D, Pg/M, Zop.D
+ /// svuint64_t svcnot[_u64]_z(svbool_t pg, svuint64_t op)
+ /// MOVPRFX Zresult.D, Pg/Z, Zop.D; CNOT Zresult.D, Pg/M, Zop.D
+ ///
+ public static unsafe Vector Cnot(Vector value) { throw new PlatformNotSupportedException(); }
+
+
+ /// Compact : Shuffle active elements of vector to the right and fill with zero
+
+ ///
+ /// svint32_t svcompact[_s32](svbool_t pg, svint32_t op)
+ /// COMPACT Zresult.S, Pg, Zop.S
+ ///
+ public static unsafe Vector Compact(Vector mask, Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svint64_t svcompact[_s64](svbool_t pg, svint64_t op)
+ /// COMPACT Zresult.D, Pg, Zop.D
+ ///
+ public static unsafe Vector Compact(Vector mask, Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint32_t svcompact[_u32](svbool_t pg, svuint32_t op)
+ /// COMPACT Zresult.S, Pg, Zop.S
+ ///
+ public static unsafe Vector Compact(Vector mask, Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svuint64_t svcompact[_u64](svbool_t pg, svuint64_t op)
+ /// COMPACT Zresult.D, Pg, Zop.D
+ ///
+ public static unsafe Vector Compact(Vector mask, Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svfloat32_t svcompact[_f32](svbool_t pg, svfloat32_t op)
+ /// COMPACT Zresult.S, Pg, Zop.S
+ ///
+ public static unsafe Vector Compact(Vector mask, Vector value) { throw new PlatformNotSupportedException(); }
+
+ ///
+ /// svfloat64_t svcompact[_f64](svbool_t pg, svfloat64_t op)
+ /// COMPACT Zresult.D, Pg, Zop.D
+ ///
+ public static unsafe Vector Compact(Vector mask, Vector value) { throw new PlatformNotSupportedException(); }
+
+
+ /// CompareEqual : Compare equal to
+
+ ///
+ /// svbool_t svcmpeq[_s8](svbool_t pg, svint8_t op1, svint8_t op2)
+ /// CMPEQ Presult.B, Pg/Z, Zop1.B, Zop2.B
+ ///
+ public static unsafe Vector CompareEqual(Vector left, Vector