From ee5caa7f8cb9c46bfcab50d4993f33efeaa1572c Mon Sep 17 00:00:00 2001
From: Steven Johnson <srj@google.com>
Date: Mon, 16 Sep 2024 15:03:38 -0700
Subject: [PATCH 1/2] Fix for top-of-tree LLVM

---
 src/LLVM_Headers.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/LLVM_Headers.h b/src/LLVM_Headers.h
index bd76de8baae6..416a62cd7390 100644
--- a/src/LLVM_Headers.h
+++ b/src/LLVM_Headers.h
@@ -85,7 +85,9 @@
 #include <llvm/Transforms/IPO.h>
 #include <llvm/Transforms/IPO/AlwaysInliner.h>
 #include <llvm/Transforms/IPO/Inliner.h>
+#if LLVM_VERSION < 200
 #include <llvm/Transforms/Instrumentation.h>
+#endif
 #include <llvm/Transforms/Instrumentation/AddressSanitizer.h>
 #include <llvm/Transforms/Instrumentation/SanitizerCoverage.h>
 #include <llvm/Transforms/Instrumentation/ThreadSanitizer.h>

From 83ec3f1b2ee96b5e66a22860a6d2933a65203a06 Mon Sep 17 00:00:00 2001
From: Steven Johnson <srj@google.com>
Date: Mon, 16 Sep 2024 16:23:47 -0700
Subject: [PATCH 2/2] Update simd_op_check_sve2.cpp

---
 test/correctness/simd_op_check_sve2.cpp | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/test/correctness/simd_op_check_sve2.cpp b/test/correctness/simd_op_check_sve2.cpp
index 9f6b958d6c2a..d0e614d657a2 100644
--- a/test/correctness/simd_op_check_sve2.cpp
+++ b/test/correctness/simd_op_check_sve2.cpp
@@ -643,8 +643,13 @@ class SimdOpCheckArmSve : public SimdOpCheckTest {
                 // No corresponding instructions exists for is_nan, is_inf, is_finite.
                 // The instructions expected to be generated depends on CodeGen_LLVM::visit(const Call *op)
                 add_arm64("nan", is_vector ? sel_op("", "fcmge", "fcmuo") : "fcmp", is_nan(f_1));
-                add_arm64("inf", {{"fabs", bits, force_vectorized_lanes}}, vf, is_inf(f_1));
-                add_arm64("finite", {{"fabs", bits, force_vectorized_lanes}}, vf, is_inf(f_1));
+                if (Halide::Internal::get_llvm_version() >= 200) {
+                    add_arm64("inf", is_vector ? sel_op("", "fcmge", "fcmeq") : "", is_inf(f_1));
+                    add_arm64("finite", is_vector ? sel_op("", "fcmge", "fcmeq") : "", is_inf(f_1));
+                } else {
+                    add_arm64("inf", {{"fabs", bits, force_vectorized_lanes}}, vf, is_inf(f_1));
+                    add_arm64("finite", {{"fabs", bits, force_vectorized_lanes}}, vf, is_inf(f_1));
+                }
             }
 
             if (bits == 16) {