diff --git a/resources/icons/branch.svg b/resources/icons/branch.svg
new file mode 100644
index 000000000..3d93e4e04
--- /dev/null
+++ b/resources/icons/branch.svg
@@ -0,0 +1,120 @@
+
+
+
+
diff --git a/resources/icons/icons.qrc b/resources/icons/icons.qrc
index bf7ac9231..7c079981d 100644
--- a/resources/icons/icons.qrc
+++ b/resources/icons/icons.qrc
@@ -7,6 +7,7 @@
server.svg
ram-memory.svg
binary-code.svg
+ branch.svg
info.svg
loadfile.svg
exit.svg
diff --git a/src/branchtab.cpp b/src/branchtab.cpp
new file mode 100644
index 000000000..a3b357b12
--- /dev/null
+++ b/src/branchtab.cpp
@@ -0,0 +1,617 @@
+#include "branchtab.h"
+#include "ui_branchtab.h"
+
+#include
+#include
+#include
+#include
+
+#include "processorhandler.h"
+#include "processors/branch/predictorhandler.h"
+#include "processors/branch/branchpredictionprocessor.h"
+#include "ripessettings.h"
+
+namespace Ripes {
+
+static QString convertToSIUnits(const double l_value, int precision = 2) {
+ QString unit;
+ double value;
+
+ if (l_value < 0) {
+ value = l_value * -1;
+ } else {
+ value = l_value;
+ }
+
+ if (value >= 1000000 && value < 1000000000) {
+ value = value / 1000000;
+ unit = "M";
+ } else if (value >= 1000 && value < 1000000) {
+ value = value / 1000;
+ unit = "K";
+ } else if (value >= 1 && value < 1000) {
+ value = value * 1;
+ } else if ((value * 1000) >= 1 && value < 1000) {
+ value = value * 1000;
+ unit = "m";
+ } else if ((value * 1000000) >= 1 && value < 1000000) {
+ value = value * 1000000;
+ unit = QChar(0x00B5);
+ } else if ((value * 1000000000) >= 1 && value < 1000000000) {
+ value = value * 1000000000;
+ unit = "n";
+ }
+
+ if (l_value > 0) {
+ return (QString::number(value, 10, precision) + " " + unit);
+ } else if (l_value < 0) {
+ return (QString::number(value * -1, 10, precision) + " " + unit);
+ }
+ return QString::number(0) + " ";
+}
+
+static bool isConditional() {
+ BranchPredictionProcessor *proc = dynamic_cast(
+ ProcessorHandler::getProcessorNonConst());
+ return proc->currentInstructionIsConditional();
+}
+
+static bool isBranch() {
+ BranchPredictionProcessor *proc = dynamic_cast(
+ ProcessorHandler::getProcessorNonConst());
+ return proc->currentInstructionIsBranch();
+}
+
+static bool isBR() {
+ return ProcessorHandler::getProcessorNonConst()->supportsBranchPrediction();
+}
+
+static uint8_t countOnes(uint16_t num) {
+ uint8_t numOnes = 0;
+ for (; num != 0; num = num >> 1) {
+ if (num & 1) {
+ numOnes++;
+ }
+ }
+ return numOnes;
+}
+
+static uint16_t getNumConditional() {
+ return PredictorHandler::getPredictor()->num_conditional;
+}
+
+static uint16_t getNumConditionalMiss() {
+ return PredictorHandler::getPredictor()->num_conditional_miss;
+}
+
+static double getConditionalAccuracy() {
+ return PredictorHandler::getPredictor()->getConditionalAccuracy();
+}
+
+static uint16_t *getLocalHistoryTable() {
+ return PredictorHandler::getPredictor()->lht.get();
+}
+
+static uint16_t *getPatternHistoryTable() {
+ return PredictorHandler::getPredictor()->pht.get();
+}
+
+static bool getPredictTaken() {
+ BranchPredictionProcessor *proc = dynamic_cast(
+ ProcessorHandler::getProcessorNonConst());
+ return proc->currentGetPrediction();
+}
+
+static void resetPredictorCounters() {
+ PredictorHandler::getPredictor()->resetPredictorCounters();
+}
+
+static void resetPredictorState() {
+ PredictorHandler::getPredictor()->resetPredictorState();
+ PredictorHandler::getPredictor()->resetPredictorCounters();
+}
+
+static void changePredictor(uint8_t predictor, uint16_t num_address_bits,
+ uint16_t num_history_bits,
+ uint16_t num_state_bits) {
+ PredictorHandler::changePredictor(predictor, num_address_bits,
+ num_history_bits, num_state_bits);
+}
+
+BranchTab::BranchTab(QToolBar *toolbar, QWidget *parent)
+ : RipesTab(toolbar, parent), m_ui(new Ui::BranchTab) {
+ m_ui->setupUi(this);
+
+ // During processor running, it should not be possible to interact with the
+ // cache tab
+ connect(ProcessorHandler::get(), &ProcessorHandler::procStateChangedNonRun,
+ this, [=] {
+ this->updateStatistics();
+ this->updateRuntimeFacts();
+ this->updateTables();
+ });
+ connect(ProcessorHandler::get(), &ProcessorHandler::processorChanged, this,
+ &BranchTab::procChanged);
+ connect(m_ui->resetCounter, &QPushButton::clicked, this, [=] {
+ resetPredictorCounters();
+ this->updateStatistics();
+ this->updateRuntimeFacts();
+ this->updateTables();
+ });
+ connect(m_ui->resetState, &QPushButton::clicked, this, [=] {
+ resetPredictorState();
+ this->updateStatistics();
+ this->updateRuntimeFacts();
+ this->updateTables();
+ });
+ connect(m_ui->predictorSelect, &QComboBox::currentIndexChanged, this,
+ [=] { this->predictorChanged(true); });
+ connect(m_ui->address_bits, &QComboBox::currentIndexChanged, this,
+ [=] { this->predictorChanged(false); });
+ connect(m_ui->history_bits, &QComboBox::currentIndexChanged, this,
+ [=] { this->predictorChanged(false); });
+ connect(m_ui->state_bits, &QComboBox::currentIndexChanged, this,
+ [=] { this->predictorChanged(false); });
+
+ // Setup statistics update timer - this timer is distinct from the
+ // ProcessorHandler's update timer, given that it needs to run during
+ // 'running' the processor.
+ m_statUpdateTimer = new QTimer(this);
+ m_statUpdateTimer->setInterval(
+ 1000.0 / RipesSettings::value(RIPES_SETTING_UIUPDATEPS).toInt());
+ connect(m_statUpdateTimer, &QTimer::timeout, this,
+ &BranchTab::updateStatistics);
+ connect(RipesSettings::getObserver(RIPES_SETTING_UIUPDATEPS),
+ &SettingObserver::modified, m_statUpdateTimer, [=] {
+ m_statUpdateTimer->setInterval(
+ 1000.0 /
+ RipesSettings::value(RIPES_SETTING_UIUPDATEPS).toInt());
+ });
+ connect(ProcessorHandler::get(), &ProcessorHandler::runStarted, this, [=] {
+ m_statUpdateTimer->start();
+ m_ui->resetCounter->setEnabled(false);
+ m_ui->resetState->setEnabled(false);
+ m_ui->predictorSelect->setEnabled(false);
+ m_ui->address_bits->setEnabled(false);
+ m_ui->history_bits->setEnabled(false);
+ m_ui->state_bits->setEnabled(false);
+ });
+ connect(ProcessorHandler::get(), &ProcessorHandler::runFinished, this, [=] {
+ m_statUpdateTimer->stop();
+ m_ui->resetCounter->setEnabled(true);
+ m_ui->resetState->setEnabled(true);
+ m_ui->predictorSelect->setEnabled(true);
+ m_ui->address_bits->setEnabled(true);
+ m_ui->history_bits->setEnabled(true);
+ m_ui->state_bits->setEnabled(true);
+ });
+
+ m_ui->splitter->setStretchFactor(0, 0);
+ m_ui->splitter->setStretchFactor(1, 10);
+ m_ui->splitter->setStretchFactor(2, 10);
+ m_ui->splitter->setSizes({1, 1000, 1000});
+
+ BranchTab::procChanged();
+}
+
+void BranchTab::tabVisibilityChanged(bool visible) {
+ if (!m_initialized && visible) {
+ m_initialized = visible;
+ }
+}
+
+void BranchTab::procChanged() {
+ if (!isBR()) {
+ this->setEnabled(false);
+ BranchTab::predictorChanged(true);
+ BranchTab::updateStatistics();
+ BranchTab::updateRuntimeFacts();
+ this->is_branch_proc = false;
+ resetPredictorState();
+ } else {
+ this->setEnabled(true);
+ this->is_branch_proc = true;
+ BranchTab::predictorChanged(true);
+ BranchTab::updateStatistics();
+ BranchTab::updateRuntimeFacts();
+ resetPredictorState();
+ }
+}
+
+void BranchTab::predictorChanged(bool is_preset) {
+ if (is_preset) {
+ int index = m_ui->predictorSelect->currentIndex();
+ switch (index) {
+ case 0:
+ this->predictor = 0; // Local Predictor
+ this->num_address_bits = 8;
+ this->num_history_bits = 8;
+ this->num_state_bits = 2;
+ m_ui->address_bits->setEnabled(true);
+ m_ui->history_bits->setEnabled(true);
+ m_ui->state_bits->setEnabled(true);
+ break;
+ case 1:
+ this->predictor = 1; // Global Predictor
+ this->num_address_bits = 0;
+ this->num_history_bits = 8;
+ this->num_state_bits = 2;
+ m_ui->address_bits->setEnabled(false);
+ m_ui->history_bits->setEnabled(true);
+ m_ui->state_bits->setEnabled(true);
+ break;
+ case 2:
+ this->predictor = 2; // Saturating Counter
+ this->num_address_bits = 0;
+ this->num_history_bits = 0;
+ this->num_state_bits = 2;
+ m_ui->address_bits->setEnabled(false);
+ m_ui->history_bits->setEnabled(false);
+ m_ui->state_bits->setEnabled(true);
+ break;
+ case 3:
+ this->predictor = 3; // Always Taken
+ this->num_address_bits = 0;
+ this->num_history_bits = 0;
+ this->num_state_bits = 0;
+ m_ui->address_bits->setEnabled(false);
+ m_ui->history_bits->setEnabled(false);
+ m_ui->state_bits->setEnabled(false);
+ break;
+ case 4:
+ this->predictor = 4; // Always Not Taken
+ this->num_address_bits = 0;
+ this->num_history_bits = 0;
+ this->num_state_bits = 0;
+ m_ui->address_bits->setEnabled(false);
+ m_ui->history_bits->setEnabled(false);
+ m_ui->state_bits->setEnabled(false);
+ break;
+ }
+ bool oldState = m_ui->address_bits->blockSignals(true);
+ m_ui->address_bits->setCurrentIndex(this->num_address_bits);
+ m_ui->address_bits->blockSignals(oldState);
+
+ oldState = m_ui->history_bits->blockSignals(true);
+ m_ui->history_bits->setCurrentIndex(this->num_history_bits);
+ m_ui->history_bits->blockSignals(oldState);
+
+ oldState = m_ui->state_bits->blockSignals(true);
+ m_ui->state_bits->setCurrentIndex(this->num_state_bits);
+ m_ui->state_bits->blockSignals(oldState);
+ }
+
+ else {
+ this->predictor = m_ui->predictorSelect->currentIndex();
+ this->num_address_bits = m_ui->address_bits->currentIndex();
+ this->num_history_bits = m_ui->history_bits->currentIndex();
+ this->num_state_bits = m_ui->state_bits->currentIndex();
+ }
+
+ changePredictor(this->predictor, this->num_address_bits,
+ this->num_history_bits, this->num_state_bits);
+
+ int num_table1_entries = 1 << this->num_address_bits;
+ int columns1 = (num_table1_entries > 8) ? 8 : num_table1_entries;
+ int rows1 = (num_table1_entries > 8) ? num_table1_entries / columns1 : 1;
+
+ int num_table2_entries = 1 << this->num_history_bits;
+ int columns2 = (num_table2_entries > 8) ? 8 : num_table2_entries;
+ int rows2 = (num_table2_entries > 8) ? num_table2_entries / columns2 : 1;
+
+ BranchTab::setupTables(rows1, columns1, rows2, columns2);
+ BranchTab::updateTables();
+ BranchTab::updateStatistics();
+ BranchTab::updateRuntimeFacts();
+}
+
+void BranchTab::updateStatistics() {
+ if (!this->is_branch_proc) {
+ return;
+ }
+
+ m_ui->numBranch->setText(QString::number(getNumConditional()));
+ m_ui->numMiss->setText(QString::number(getNumConditionalMiss()));
+ double accuracy = getConditionalAccuracy();
+ if (isnan(accuracy)) {
+ accuracy = 0;
+ }
+ m_ui->branchAccuracy->setText(QString::number(accuracy, 'g', 5) + "%");
+
+ static auto lastUpdateTime = std::chrono::system_clock::now();
+ static long long lastCycleCount =
+ ProcessorHandler::getProcessor()->getCycleCount();
+
+ const auto timeNow = std::chrono::system_clock::now();
+ const auto cycleCount = ProcessorHandler::getProcessor()->getCycleCount();
+ const auto instrsRetired =
+ ProcessorHandler::getProcessor()->getInstructionsRetired();
+ const auto timeDiff = std::chrono::duration_cast(
+ timeNow - lastUpdateTime)
+ .count() /
+ 1000.0; // in seconds
+ const auto cycleDiff = cycleCount - lastCycleCount;
+
+ // Cycle count
+ m_ui->cycles->setText(QString::number(cycleCount));
+ // Instructions retired
+ m_ui->instrsRetired->setText(QString::number(instrsRetired));
+ QString cpiText, ipcText;
+ if (cycleCount != 0 && instrsRetired != 0) {
+ const double cpi =
+ static_cast(cycleCount) / static_cast(instrsRetired);
+ const double ipc = 1 / cpi;
+ cpiText = QString::number(cpi, 'g', 3);
+ ipcText = QString::number(ipc, 'g', 3);
+ }
+ // CPI & IPC
+ m_ui->cpi->setText(cpiText);
+ m_ui->ipc->setText(ipcText);
+
+ // Clock rate
+ const double clockRate = static_cast(cycleDiff) / timeDiff;
+ m_ui->clockRate->setText(convertToSIUnits(clockRate) + "Hz");
+
+ // Record timestamp values
+ lastUpdateTime = timeNow;
+ lastCycleCount = cycleCount;
+}
+
+void BranchTab::updateRuntimeFacts() {
+ if (!this->is_branch_proc) {
+ return;
+ }
+
+ const RipesProcessor *proc = ProcessorHandler::getProcessor();
+ AInt addr = proc->getPcForStage({0, 0});
+ m_ui->currPC->setText("0x" + QString::number(addr, 16));
+ QString inst = ProcessorHandler::disassembleInstr(addr);
+ m_ui->currInst->setText(inst);
+
+ if (!isBR()) {
+ m_ui->isBranch->setStyleSheet("QLineEdit"
+ "{"
+ "background: rgb(255, 255, 255)"
+ "}");
+ m_ui->isJump->setStyleSheet("QLineEdit"
+ "{"
+ "background: rgb(255, 255, 255)"
+ "}");
+ m_ui->predictTaken->setStyleSheet("QLineEdit"
+ "{"
+ "background: rgb(255, 255, 255)"
+ "}");
+ m_ui->lhtEntry->setText("");
+ m_ui->phtEntry->setText("");
+ return;
+ }
+
+ if (isConditional()) {
+ m_ui->isBranch->setStyleSheet("QLineEdit"
+ "{"
+ "background: rgb(128, 255, 128)"
+ "}");
+ uint16_t *lht = getLocalHistoryTable();
+ uint16_t *pht = getPatternHistoryTable();
+ if (lht == nullptr) {
+ m_ui->lhtEntry->setText("");
+ }
+ uint16_t lht_entry = lht[(addr >> 2) & ((1 << this->num_address_bits) - 1)];
+ uint16_t pht_entry = pht[lht_entry];
+ m_ui->lhtEntry->setText(QStringLiteral("%1").arg(
+ lht_entry, this->num_history_bits, 2, QLatin1Char('0')));
+ m_ui->phtEntry->setText(QStringLiteral("%1").arg(
+ pht_entry, this->num_state_bits, 2, QLatin1Char('0')));
+ } else {
+ m_ui->isBranch->setStyleSheet("QLineEdit"
+ "{"
+ "background: rgb(255, 128, 128)"
+ "}");
+ m_ui->lhtEntry->setText("");
+ m_ui->phtEntry->setText("");
+ }
+
+ if (isBranch() && !isConditional()) {
+ m_ui->isJump->setStyleSheet("QLineEdit"
+ "{"
+ "background: rgb(128, 255, 128)"
+ "}");
+ } else {
+ m_ui->isJump->setStyleSheet("QLineEdit"
+ "{"
+ "background: rgb(255, 128, 128)"
+ "}");
+ }
+
+ if (getPredictTaken()) {
+ m_ui->predictTaken->setStyleSheet("QLineEdit"
+ "{"
+ "background: rgb(128, 255, 128)"
+ "}");
+ } else {
+ m_ui->predictTaken->setStyleSheet("QLineEdit"
+ "{"
+ "background: rgb(255, 128, 128)"
+ "}");
+ }
+}
+
+void BranchTab::setupTables(int rows1, int columns1, int rows2, int columns2) {
+ if (!this->is_branch_proc) {
+ return;
+ }
+
+ this->table1_rows = rows1;
+ this->table1_columns = columns1;
+ this->table2_rows = rows2;
+ this->table2_columns = columns2;
+
+ m_ui->table1->setRowCount(rows1 + 1);
+ m_ui->table1->setColumnCount(columns1 + 1);
+ for (int i = 0; i < rows1 + 1; i++) {
+ m_ui->table1->setRowHeight(i, 20);
+ }
+ for (int i = 1; i < rows1 + 1; i++) {
+ QTableWidgetItem *item = new QTableWidgetItem(
+ "0x" + QString::number((i - 1) * columns1 * 4, 16));
+ item->setTextAlignment(Qt::AlignRight);
+ m_ui->table1->setItem(i, 0, item);
+ }
+ for (int i = 0; i < columns1 + 1; i++) {
+ m_ui->table1->setColumnWidth(i, 70);
+ }
+ for (int i = 1; i < columns1 + 1; i++) {
+ QTableWidgetItem *item =
+ new QTableWidgetItem("0x" + QString::number((i - 1) * 4, 16));
+ item->setTextAlignment(Qt::AlignHCenter);
+ m_ui->table1->setItem(0, i, item);
+ }
+
+ m_ui->table2->setRowCount(rows2 + 1);
+ m_ui->table2->setColumnCount(columns2 + 1);
+ for (int i = 0; i < rows2 + 1; i++) {
+ m_ui->table2->setRowHeight(i, 20);
+ }
+ for (int i = 1; i < rows2 + 1; i++) {
+ QTableWidgetItem *item = new QTableWidgetItem(QStringLiteral("%1").arg(
+ (i - 1) * columns2, (int)log2(rows2 * columns2), 2, QLatin1Char('0')));
+ item->setTextAlignment(Qt::AlignRight);
+ m_ui->table2->setItem(i, 0, item);
+ }
+ for (int i = 0; i < columns2 + 1; i++) {
+ m_ui->table2->setColumnWidth(i, 70);
+ }
+ for (int i = 1; i < columns2 + 1; i++) {
+ QTableWidgetItem *item = new QTableWidgetItem(QStringLiteral("%1").arg(
+ (i - 1), (int)log2(columns2), 2, QLatin1Char('0')));
+ item->setTextAlignment(Qt::AlignHCenter);
+ m_ui->table2->setItem(0, i, item);
+ }
+}
+
+void BranchTab::updateTables() {
+ if (!this->is_branch_proc) {
+ return;
+ }
+
+ QBrush brush_snt(QColor(255, 128, 128));
+ QBrush brush_wnt(QColor(255, 192, 192));
+ QBrush brush_wt(QColor(192, 255, 192));
+ QBrush brush_st(QColor(128, 255, 128));
+
+ uint16_t *lht = getLocalHistoryTable();
+ uint16_t *pht = getPatternHistoryTable();
+
+ if (!lht || !pht) {
+ for (int i = 1; i < this->table1_rows + 1; i++) {
+ for (int j = 1; j < this->table1_columns + 1; j++) {
+ uint16_t lht_entry = 0;
+
+ QTableWidgetItem *item = new QTableWidgetItem(QStringLiteral("%1").arg(
+ lht_entry, this->num_history_bits, 2, QLatin1Char('0')));
+ item->setTextAlignment(Qt::AlignHCenter);
+ m_ui->table1->setItem(i, j, item);
+ }
+ }
+ for (int i = 1; i < this->table2_rows + 1; i++) {
+ for (int j = 1; j < this->table2_columns + 1; j++) {
+ uint16_t pht_entry = 0;
+
+ QTableWidgetItem *item = new QTableWidgetItem(QStringLiteral("%1").arg(
+ pht_entry, this->num_state_bits, 2, QLatin1Char('0')));
+ item->setTextAlignment(Qt::AlignHCenter);
+ m_ui->table2->setItem(i, j, item);
+ }
+ }
+ } else {
+ for (int i = 1; i < this->table1_rows + 1; i++) {
+ for (int j = 1; j < this->table1_columns + 1; j++) {
+ uint16_t lht_entry = lht[(j - 1) + this->table1_columns * (i - 1)];
+
+ QTableWidgetItem *item = new QTableWidgetItem(QStringLiteral("%1").arg(
+ lht_entry, this->num_history_bits, 2, QLatin1Char('0')));
+ item->setTextAlignment(Qt::AlignHCenter);
+
+ m_ui->table1->setItem(i, j, item);
+
+ if (this->num_history_bits % 2 == 0) {
+ int num_ones = countOnes(lht_entry);
+ int step = 0;
+ if (this->num_history_bits == 0) {
+ step = 128;
+ } else {
+ step = 128 / (this->num_history_bits / 2);
+ }
+
+ if (num_ones == this->num_history_bits / 2) {
+ m_ui->table1->item(i, j)->setBackground(
+ QBrush(QColor(255, 255, 255)));
+ }
+
+ else if (num_ones < this->num_history_bits / 2) {
+ int num_steps = num_ones;
+ m_ui->table1->item(i, j)->setBackground(QBrush(
+ QColor(255, 128 + num_steps * step, 128 + num_steps * step)));
+ }
+
+ else {
+ int num_steps = this->num_history_bits - num_ones;
+ m_ui->table1->item(i, j)->setBackground(QBrush(
+ QColor(128 + num_steps * step, 255, 128 + num_steps * step)));
+ }
+ }
+
+ else {
+ int num_ones = countOnes(lht_entry);
+ int step = 128 / ((this->num_history_bits + 1) / 2);
+
+ if (num_ones <= this->num_history_bits / 2) {
+ int num_steps = num_ones;
+ m_ui->table1->item(i, j)->setBackground(QBrush(
+ QColor(255, 128 + num_steps * step, 128 + num_steps * step)));
+ }
+
+ else {
+ int num_steps = this->num_history_bits - num_ones;
+ m_ui->table1->item(i, j)->setBackground(QBrush(
+ QColor(128 + num_steps * step, 255, 128 + num_steps * step)));
+ }
+ }
+ }
+ }
+ for (int i = 1; i < this->table2_rows + 1; i++) {
+ for (int j = 1; j < this->table2_columns + 1; j++) {
+ uint16_t pht_entry = pht[(j - 1) + this->table2_columns * (i - 1)];
+
+ QTableWidgetItem *item = new QTableWidgetItem(QStringLiteral("%1").arg(
+ pht_entry, this->num_state_bits, 2, QLatin1Char('0')));
+ item->setTextAlignment(Qt::AlignHCenter);
+
+ m_ui->table2->setItem(i, j, item);
+
+ if (this->predictor == 4) {
+ m_ui->table2->item(i, j)->setBackground(
+ QBrush(QColor(255, 128, 128)));
+ } else {
+ int step = 128 / (1 << (this->num_state_bits - 1));
+
+ if (pht_entry < (1 << (this->num_state_bits - 1))) {
+ int num_steps = pht_entry;
+ m_ui->table2->item(i, j)->setBackground(QBrush(
+ QColor(255, 128 + num_steps * step, 128 + num_steps * step)));
+ }
+
+ else {
+ int num_steps = ((1 << this->num_state_bits) - 1) - pht_entry;
+ m_ui->table2->item(i, j)->setBackground(QBrush(
+ QColor(128 + num_steps * step, 255, 128 + num_steps * step)));
+ }
+ }
+ }
+ }
+ }
+}
+
+BranchTab::~BranchTab() { delete m_ui; }
+
+} // namespace Ripes
diff --git a/src/branchtab.h b/src/branchtab.h
new file mode 100644
index 000000000..d178e8a08
--- /dev/null
+++ b/src/branchtab.h
@@ -0,0 +1,53 @@
+#pragma once
+
+#include "ripestab.h"
+#include
+
+#include "ripes_types.h"
+
+namespace Ripes {
+
+namespace Ui {
+class BranchTab;
+}
+
+class BranchTab : public RipesTab {
+ Q_OBJECT
+
+public:
+ explicit BranchTab(QToolBar *toolbar, QWidget *parent = nullptr);
+ ~BranchTab() override;
+
+ void tabVisibilityChanged(bool visible) override;
+
+ void updateStatistics();
+
+ void updateRuntimeFacts();
+
+ void setupTables(int rows1, int colums1, int rows2, int columns2);
+
+ void updateTables();
+
+ void procChanged();
+
+ void predictorChanged(bool is_preset);
+
+signals:
+ void focusAddressChanged(Ripes::AInt address);
+
+private:
+ Ui::BranchTab *m_ui;
+ bool m_initialized = false;
+ QTimer *m_statUpdateTimer;
+ int table1_rows = 0;
+ int table1_columns = 0;
+ int table2_rows = 0;
+ int table2_columns = 0;
+ uint16_t num_address_bits = 0;
+ uint16_t num_history_bits = 0;
+ uint16_t num_state_bits = 0;
+ bool is_branch_proc = true;
+ uint8_t predictor = 0;
+};
+
+} // namespace Ripes
diff --git a/src/branchtab.ui b/src/branchtab.ui
new file mode 100644
index 000000000..6adf031b3
--- /dev/null
+++ b/src/branchtab.ui
@@ -0,0 +1,650 @@
+
+
+ Ripes::BranchTab
+
+
+
+ 0
+ 0
+ 761
+ 751
+
+
+
+ Form
+
+
+
+ 0
+
+
+ 6
+
+
+ 0
+
+
+ 0
+
+ -
+
+
+ Qt::Horizontal
+
+
+ false
+
+
+
+
-
+
+
+ QLayout::SetDefaultConstraint
+
+
-
+
+
+ Instr. PHT Entry:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
-
+
+ Local Predictor
+
+
+ -
+
+ Global Predictor
+
+
+ -
+
+ Saturating Counter
+
+
+ -
+
+ Always Taken
+
+
+ -
+
+ Always Not Taken
+
+
+
+
+ -
+
+
+ IPC:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
+ Reset Predictor State
+
+
+
+ -
+
+
+ Qt::Vertical
+
+
+
+ 20
+ 40
+
+
+
+
+ -
+
+
+ Current PC:
+
+
+ Qt::AlignCenter
+
+
+
+ -
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+ true
+
+
+
+ -
+
+
+ Cycles:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
+ Misses:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
+ Current Instruction:
+
+
+ Qt::AlignCenter
+
+
+
+ -
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+ true
+
+
+
+ -
+
+
+ Reset Branch/Miss Counter
+
+
+
+ -
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+ true
+
+
+
+ -
+
+
+ Address Bits:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+ true
+
+
+
+ -
+
+
+ Accuracy:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
+ Instr. LHT Entry:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
+ Predict Taken
+
+
+ Qt::AlignCenter
+
+
+ true
+
+
+
+ -
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+ true
+
+
+
+ -
+
+
+ Predictor Preset:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
+ Clock Rate:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+ true
+
+
+
+ -
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+ true
+
+
+
+ -
+
+
+ Conditional
+
+
+ Qt::AlignCenter
+
+
+ true
+
+
+
+ -
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+ true
+
+
+
+ -
+
+
+ Unconditional
+
+
+ Qt::AlignCenter
+
+
+ true
+
+
+
+ -
+
+
+ History Bits:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+ true
+
+
+
+ -
+
+
+ Qt::AlignCenter
+
+
+ true
+
+
+
+ -
+
+
+ Instrs. Retired:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
+ Branches:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+ true
+
+
+
+ -
+
+
+ Execution Info:
+
+
+ Qt::AlignCenter
+
+
+
+ -
+
+
+ Qt::AlignCenter
+
+
+ true
+
+
+
+ -
+
+
+ Qt::Horizontal
+
+
+ QSizePolicy::Fixed
+
+
+
+ 400
+ 20
+
+
+
+
+ -
+
+
+ CPI:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
+ State Bits:
+
+
+ Qt::AlignRight|Qt::AlignTrailing|Qt::AlignVCenter
+
+
+
+ -
+
+
-
+
+ 0
+
+
+ -
+
+ 1
+
+
+ -
+
+ 2
+
+
+ -
+
+ 3
+
+
+ -
+
+ 4
+
+
+ -
+
+ 5
+
+
+ -
+
+ 6
+
+
+ -
+
+ 7
+
+
+ -
+
+ 8
+
+
+
+
+ -
+
+
-
+
+ 0
+
+
+ -
+
+ 1
+
+
+ -
+
+ 2
+
+
+ -
+
+ 3
+
+
+ -
+
+ 4
+
+
+ -
+
+ 5
+
+
+ -
+
+ 6
+
+
+ -
+
+ 7
+
+
+ -
+
+ 8
+
+
+
+
+ -
+
+
-
+
+ 0
+
+
+ -
+
+ 1
+
+
+ -
+
+ 2
+
+
+ -
+
+ 3
+
+
+ -
+
+ 4
+
+
+ -
+
+ 5
+
+
+ -
+
+ 6
+
+
+ -
+
+ 7
+
+
+ -
+
+ 8
+
+
+
+
+
+
+
+
+
+
+ -
+
+
+ Local History Table
+
+
+ Qt::AlignCenter
+
+
+
+ -
+
+
+ false
+
+
+ false
+
+
+
+
+
+
+
+ -
+
+
+ false
+
+
+ false
+
+
+
+ -
+
+
+ Pattern History Table
+
+
+ Qt::AlignCenter
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/mainwindow.cpp b/src/mainwindow.cpp
index fdc7297a5..05fc90e06 100644
--- a/src/mainwindow.cpp
+++ b/src/mainwindow.cpp
@@ -1,6 +1,7 @@
#include "mainwindow.h"
#include "ui_mainwindow.h"
+#include "branchtab.h"
#include "cachetab.h"
#include "edittab.h"
#include "iotab.h"
@@ -90,12 +91,19 @@ MainWindow::MainWindow(QWidget *parent)
m_stackedTabs->insertWidget(IOTabID, IOTab);
m_tabWidgets[IOTabID] = {IOTab, IOToolbar};
+ auto *BranchToolbar = addToolBar("Branch");
+ BranchToolbar->setVisible(false);
+ auto *BranchTab = new class BranchTab(BranchToolbar, this);
+ m_stackedTabs->insertWidget(BranchTabID, BranchTab);
+ m_tabWidgets[BranchTabID] = {BranchTab, BranchToolbar};
+
// Setup tab bar
m_ui->tabbar->addFancyTab(QIcon(":/icons/binary-code.svg"), "Editor");
m_ui->tabbar->addFancyTab(QIcon(":/icons/cpu.svg"), "Processor");
m_ui->tabbar->addFancyTab(QIcon(":/icons/server.svg"), "Cache");
m_ui->tabbar->addFancyTab(QIcon(":/icons/ram-memory.svg"), "Memory");
m_ui->tabbar->addFancyTab(QIcon(":/icons/led.svg"), "I/O");
+ m_ui->tabbar->addFancyTab(QIcon(":/icons/branch.svg"), "Branch");
connect(m_ui->tabbar, &FancyTabBar::activeIndexChanged, this,
&MainWindow::tabChanged);
connect(m_ui->tabbar, &FancyTabBar::activeIndexChanged, m_stackedTabs,
diff --git a/src/mainwindow.h b/src/mainwindow.h
index 044d9d7cf..125caaed8 100644
--- a/src/mainwindow.h
+++ b/src/mainwindow.h
@@ -37,6 +37,7 @@ class MainWindow : public QMainWindow {
CacheTabID,
MemoryTabID,
IOTabID,
+ BranchTabID,
NTabsID
};
diff --git a/src/processorregistry.cpp b/src/processorregistry.cpp
index 4b82e91df..18d00d5cc 100644
--- a/src/processorregistry.cpp
+++ b/src/processorregistry.cpp
@@ -3,6 +3,7 @@
#include
#include "processors/RISC-V/rv5s/rv5s.h"
+#include "processors/RISC-V/rv5s_br/rv5s_br.h"
#include "processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h"
#include "processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h"
#include "processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h"
@@ -31,6 +32,9 @@ constexpr const char rv5s_no_hz_desc[] =
constexpr const char rv5s_desc[] =
"A 5-stage in-order processor with hazard detection/elimination and "
"forwarding.";
+constexpr const char rv5s_br_desc[] =
+ "A 5-stage in-order processor with hazard detection/elimination, "
+ "forwarding, and branch prediction.";
constexpr const char rv5s_no_fw_desc[] =
"A 5-stage in-order processor with hazard detection/elimination but no "
"forwarding unit.";
@@ -156,6 +160,22 @@ ProcessorRegistry::ProcessorRegistry() {
ProcessorID::RV64_5S, "5-stage processor", rv5s_desc, layouts,
defRegVals));
+ // RISC-V 5-stage w/ branch prediction
+ layouts = {{"Extended",
+ ":/layouts/RISC-V/rv5s_br/rv5s_br_extended_layout.json",
+ {{{0, 0}, QPointF{0.08, 0}},
+ {{0, 1}, QPointF{0.28, 0}},
+ {{0, 2}, QPointF{0.54, 0}},
+ {{0, 3}, QPointF{0.78, 0}},
+ {{0, 4}, QPointF{0.9, 0}}}}};
+ defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
+ addProcessor(ProcInfo>(
+ ProcessorID::RV32_5S_BR, "5-stage processor w/ branch prediction",
+ rv5s_br_desc, layouts, defRegVals));
+ addProcessor(ProcInfo>(
+ ProcessorID::RV64_5S_BR, "5-stage processor w/ branch prediction",
+ rv5s_br_desc, layouts, defRegVals));
+
// RISC-V 6-stage dual issue
layouts = {{"Extended",
":/layouts/RISC-V/rv6s_dual/rv6s_dual_extended_layout.json",
diff --git a/src/processorregistry.h b/src/processorregistry.h
index c057d20e9..def3485bf 100644
--- a/src/processorregistry.h
+++ b/src/processorregistry.h
@@ -26,12 +26,14 @@ enum ProcessorID {
RV32_5S_NO_HZ,
RV32_5S_NO_FW,
RV32_5S,
+ RV32_5S_BR,
RV32_6S_DUAL,
RV64_SS,
RV64_5S_NO_FW_HZ,
RV64_5S_NO_HZ,
RV64_5S_NO_FW,
RV64_5S,
+ RV64_5S_BR,
RV64_6S_DUAL,
NUM_PROCESSORS
};
diff --git a/src/processors/CMakeLists.txt b/src/processors/CMakeLists.txt
index 4359f71e2..7695e0d3c 100644
--- a/src/processors/CMakeLists.txt
+++ b/src/processors/CMakeLists.txt
@@ -54,6 +54,7 @@ endmacro()
create_isa_lib(RISC-V)
create_vsrtl_processor(RISC-V rvss)
create_vsrtl_processor(RISC-V rv5s)
+create_vsrtl_processor(RISC-V rv5s_br)
create_vsrtl_processor(RISC-V rv5s_no_fw_hz)
create_vsrtl_processor(RISC-V rv5s_no_hz)
create_vsrtl_processor(RISC-V rv5s_no_fw)
diff --git a/src/processors/RISC-V/rv5s/rv5s.h b/src/processors/RISC-V/rv5s/rv5s.h
index f298c5641..1d54e2f05 100644
--- a/src/processors/RISC-V/rv5s/rv5s.h
+++ b/src/processors/RISC-V/rv5s/rv5s.h
@@ -531,6 +531,8 @@ class RV5S : public RipesVSRTLProcessor {
return rfs;
}
+ bool supportsBranchPrediction() const override { return false; }
+
private:
/**
* @brief m_syscallExitCycle
diff --git a/src/processors/RISC-V/rv5s_br/rv5s_br.h b/src/processors/RISC-V/rv5s_br/rv5s_br.h
new file mode 100644
index 000000000..8c39bb18e
--- /dev/null
+++ b/src/processors/RISC-V/rv5s_br/rv5s_br.h
@@ -0,0 +1,710 @@
+#pragma once
+
+#include "VSRTL/core/vsrtl_adder.h"
+#include "VSRTL/core/vsrtl_comparator.h"
+#include "VSRTL/core/vsrtl_constant.h"
+#include "VSRTL/core/vsrtl_design.h"
+#include "VSRTL/core/vsrtl_logicgate.h"
+#include "VSRTL/core/vsrtl_multiplexer.h"
+
+#include "../../branch/branchpredictionprocessor.h"
+#include "../../ripesvsrtlprocessor.h"
+
+// Functional units
+#include "../riscv.h"
+#include "../rv_alu.h"
+#include "../rv_branch.h"
+#include "../rv_control.h"
+#include "../rv_decode.h"
+#include "../rv_ecallchecker.h"
+#include "../rv_immediate.h"
+#include "../rv_memory.h"
+#include "../rv_registerfile.h"
+#include "../rv_uncompress.h"
+
+// Stage separating registers
+#include "../rv5s/rv5s_exmem.h"
+#include "../rv5s/rv5s_idex.h"
+#include "../rv5s/rv5s_memwb.h"
+#include "../rv5s_no_fw_hz/rv5s_no_fw_hz_ifid.h"
+
+// Forwarding & Hazard detection unit
+#include "../rv5s/rv5s_forwardingunit.h"
+#include "../rv5s/rv5s_hazardunit.h"
+
+// Branch prediction unit
+#include "../../branch/predictorhandler.h"
+#include "rv5s_branch_miss.h"
+#include "rv5s_branch_nextpc.h"
+#include "rv5s_branch_regs.h"
+#include "rv5s_branchunit.h"
+
+namespace vsrtl {
+namespace core {
+using namespace Ripes;
+
+template
+class RV5S_BR : public RipesVSRTLProcessor, public BranchPredictionProcessor {
+ static_assert(std::is_same::value ||
+ std::is_same::value,
+ "Only supports 32- and 64-bit variants");
+ static constexpr unsigned XLEN = sizeof(XLEN_T) * CHAR_BIT;
+
+public:
+ enum Stage { IF = 0, ID = 1, EX = 2, MEM = 3, WB = 4, STAGECOUNT };
+ RV5S_BR(const QStringList &extensions)
+ : RipesVSRTLProcessor("5-Stage RISC-V Processor") {
+ m_enabledISA = std::make_shared()>>(extensions);
+ decode->setISA(m_enabledISA);
+ uncompress->setISA(m_enabledISA);
+
+ // -----------------------------------------------------------------------
+ // Program counter
+ pc_reg->out >> pc_4->op1;
+ pc_inc->out >> pc_4->op2;
+ br_nextpc->curr_next >> pc_reg->in;
+ 0 >> pc_reg->clear;
+ br_pc_or->out >> pc_reg->enable;
+
+ 2 >> pc_inc->get(PcInc::INC2);
+ 4 >> pc_inc->get(PcInc::INC4);
+ uncompress->Pc_Inc >> pc_inc->select;
+
+ 0 >> *efsc_or->in[0];
+ ecallChecker->syscallExit >> *efsc_or->in[1];
+
+ efsc_or->out >> *efschz_or->in[0];
+ hzunit->hazardIDEXClear >> *efschz_or->in[1];
+
+ // -----------------------------------------------------------------------
+ // Instruction memory
+ pc_reg->out >> instr_mem->addr;
+ instr_mem->setMemory(m_memory);
+
+ // -----------------------------------------------------------------------
+ // Decode
+ ifid_reg->instr_out >> decode->instr;
+
+ // -----------------------------------------------------------------------
+ // Control signals
+ decode->opcode >> control->opcode;
+
+ // -----------------------------------------------------------------------
+ // Immediate
+ decode->opcode >> immediate->opcode;
+ ifid_reg->instr_out >> immediate->instr;
+
+ // -----------------------------------------------------------------------
+ // Registers
+ decode->r1_reg_idx >> registerFile->r1_addr;
+ decode->r2_reg_idx >> registerFile->r2_addr;
+ reg_wr_src->out >> registerFile->data_in;
+
+ memwb_reg->wr_reg_idx_out >> registerFile->wr_addr;
+ memwb_reg->reg_do_write_out >> registerFile->wr_en;
+ memwb_reg->mem_read_out >> reg_wr_src->get(RegWrSrc::MEMREAD);
+ memwb_reg->alures_out >> reg_wr_src->get(RegWrSrc::ALURES);
+ memwb_reg->pc4_out >> reg_wr_src->get(RegWrSrc::PC4);
+ memwb_reg->reg_wr_src_ctrl_out >> reg_wr_src->select;
+
+ registerFile->setMemory(m_regMem);
+
+ // -----------------------------------------------------------------------
+ // Branch
+ idex_reg->br_op_out >> branch->comp_op;
+ reg1_fw_src->out >> branch->op1;
+ reg2_fw_src->out >> branch->op2;
+
+ // -----------------------------------------------------------------------
+ // ALU
+
+ // Forwarding multiplexers
+ idex_reg->r1_out >> reg1_fw_src->get(ForwardingSrc::IdStage);
+ exmem_reg->alures_out >>
+ reg1_fw_src->get(
+ ForwardingSrc::MemStage); // Todo: Mem stage needs a mux to allow
+ // for AUIPC forwarding
+ reg_wr_src->out >> reg1_fw_src->get(ForwardingSrc::WbStage);
+ funit->alu_reg1_forwarding_ctrl >> reg1_fw_src->select;
+
+ idex_reg->r2_out >> reg2_fw_src->get(ForwardingSrc::IdStage);
+ exmem_reg->alures_out >> reg2_fw_src->get(ForwardingSrc::MemStage);
+ reg_wr_src->out >> reg2_fw_src->get(ForwardingSrc::WbStage);
+ funit->alu_reg2_forwarding_ctrl >> reg2_fw_src->select;
+
+ // ALU operand multiplexers
+ reg1_fw_src->out >> alu_op1_src->get(AluSrc1::REG1);
+ idex_reg->pc_out >> alu_op1_src->get(AluSrc1::PC);
+ idex_reg->alu_op1_ctrl_out >> alu_op1_src->select;
+
+ reg2_fw_src->out >> alu_op2_src->get(AluSrc2::REG2);
+ idex_reg->imm_out >> alu_op2_src->get(AluSrc2::IMM);
+ idex_reg->alu_op2_ctrl_out >> alu_op2_src->select;
+
+ alu_op1_src->out >> alu->op1;
+ alu_op2_src->out >> alu->op2;
+
+ idex_reg->alu_ctrl_out >> alu->ctrl;
+
+ // -----------------------------------------------------------------------
+ // Data memory
+ exmem_reg->alures_out >> data_mem->addr;
+ exmem_reg->mem_do_write_out >> data_mem->wr_en;
+ exmem_reg->r2_out >> data_mem->data_in;
+ exmem_reg->mem_op_out >> data_mem->op;
+ data_mem->mem->setMemory(m_memory);
+
+ // -----------------------------------------------------------------------
+ // Ecall checker
+
+ idex_reg->opcode_out >> ecallChecker->opcode;
+ ecallChecker->setSyscallCallback(&trapHandler);
+ hzunit->stallEcallHandling >> ecallChecker->stallEcallHandling;
+
+ // -----------------------------------------------------------------------
+ // IF/ID
+ pc_4->out >> ifid_reg->pc4_in;
+ pc_reg->out >> ifid_reg->pc_in;
+ uncompress->exp_instr >> ifid_reg->instr_in;
+ hzunit->hazardFEEnable >> ifid_reg->enable;
+ efsc_or->out >> *ifid_reg_clear_or->in[1];
+ 1 >> ifid_reg->valid_in; // Always valid unless register is cleared
+
+ // -----------------------------------------------------------------------
+ // Increment
+ instr_mem->data_out >> uncompress->instr;
+
+ // -----------------------------------------------------------------------
+ // ID/EX
+ hzunit->hazardIDEXEnable >> idex_reg->enable;
+ hzunit->hazardIDEXClear >> idex_reg->stalled_in;
+ efschz_or->out >> *idex_reg_clear_or->in[1];
+
+ // Data
+ ifid_reg->pc4_out >> idex_reg->pc4_in;
+ ifid_reg->pc_out >> idex_reg->pc_in;
+ registerFile->r1_out >> idex_reg->r1_in;
+ registerFile->r2_out >> idex_reg->r2_in;
+ immediate->imm >> idex_reg->imm_in;
+
+ // Control
+ decode->wr_reg_idx >> idex_reg->wr_reg_idx_in;
+ control->reg_wr_src_ctrl >> idex_reg->reg_wr_src_ctrl_in;
+ control->reg_do_write_ctrl >> idex_reg->reg_do_write_in;
+ control->alu_op1_ctrl >> idex_reg->alu_op1_ctrl_in;
+ control->alu_op2_ctrl >> idex_reg->alu_op2_ctrl_in;
+ control->mem_do_write_ctrl >> idex_reg->mem_do_write_in;
+ control->alu_ctrl >> idex_reg->alu_ctrl_in;
+ control->mem_ctrl >> idex_reg->mem_op_in;
+ control->comp_ctrl >> idex_reg->br_op_in;
+ control->do_branch >> idex_reg->do_br_in;
+ control->do_jump >> idex_reg->do_jmp_in;
+ decode->r1_reg_idx >> idex_reg->rd_reg1_idx_in;
+ decode->r2_reg_idx >> idex_reg->rd_reg2_idx_in;
+ decode->opcode >> idex_reg->opcode_in;
+ control->mem_do_read_ctrl >> idex_reg->mem_do_read_in;
+
+ ifid_reg->valid_out >> idex_reg->valid_in;
+
+ // -----------------------------------------------------------------------
+ // EX/MEM
+ 1 >> exmem_reg->enable;
+ hzunit->hazardEXMEMClear >> exmem_reg->clear;
+ hzunit->hazardEXMEMClear >> *mem_stalled_or->in[0];
+ idex_reg->stalled_out >> *mem_stalled_or->in[1];
+ mem_stalled_or->out >> exmem_reg->stalled_in;
+
+ // Data
+ idex_reg->pc_out >> exmem_reg->pc_in;
+ idex_reg->pc4_out >> exmem_reg->pc4_in;
+ reg2_fw_src->out >> exmem_reg->r2_in;
+ alu->res >> exmem_reg->alures_in;
+
+ // Control
+ idex_reg->reg_wr_src_ctrl_out >> exmem_reg->reg_wr_src_ctrl_in;
+ idex_reg->wr_reg_idx_out >> exmem_reg->wr_reg_idx_in;
+ idex_reg->reg_do_write_out >> exmem_reg->reg_do_write_in;
+ idex_reg->mem_do_write_out >> exmem_reg->mem_do_write_in;
+ idex_reg->mem_do_read_out >> exmem_reg->mem_do_read_in;
+ idex_reg->mem_op_out >> exmem_reg->mem_op_in;
+
+ idex_reg->valid_out >> exmem_reg->valid_in;
+
+ // -----------------------------------------------------------------------
+ // MEM/WB
+
+ exmem_reg->stalled_out >> memwb_reg->stalled_in;
+
+ // Data
+ exmem_reg->pc_out >> memwb_reg->pc_in;
+ exmem_reg->pc4_out >> memwb_reg->pc4_in;
+ exmem_reg->alures_out >> memwb_reg->alures_in;
+ data_mem->data_out >> memwb_reg->mem_read_in;
+
+ // Control
+ exmem_reg->reg_wr_src_ctrl_out >> memwb_reg->reg_wr_src_ctrl_in;
+ exmem_reg->wr_reg_idx_out >> memwb_reg->wr_reg_idx_in;
+ exmem_reg->reg_do_write_out >> memwb_reg->reg_do_write_in;
+
+ exmem_reg->valid_out >> memwb_reg->valid_in;
+
+ // -----------------------------------------------------------------------
+ // Forwarding unit
+ idex_reg->rd_reg1_idx_out >> funit->id_reg1_idx;
+ idex_reg->rd_reg2_idx_out >> funit->id_reg2_idx;
+
+ exmem_reg->wr_reg_idx_out >> funit->mem_reg_wr_idx;
+ exmem_reg->reg_do_write_out >> funit->mem_reg_wr_en;
+
+ memwb_reg->wr_reg_idx_out >> funit->wb_reg_wr_idx;
+ memwb_reg->reg_do_write_out >> funit->wb_reg_wr_en;
+
+ // -----------------------------------------------------------------------
+ // Hazard detection unit
+ decode->r1_reg_idx >> hzunit->id_reg1_idx;
+ decode->r2_reg_idx >> hzunit->id_reg2_idx;
+
+ idex_reg->mem_do_read_out >> hzunit->ex_do_mem_read_en;
+ idex_reg->wr_reg_idx_out >> hzunit->ex_reg_wr_idx;
+
+ exmem_reg->reg_do_write_out >> hzunit->mem_do_reg_write;
+
+ memwb_reg->reg_do_write_out >> hzunit->wb_do_reg_write;
+
+ idex_reg->opcode_out >> hzunit->opcode;
+
+ // -----------------------------------------------------------------------
+ // Branch prediction unit
+ brunit->setProc(dynamic_cast(this));
+ pc_reg->out >> brunit->curr_pc;
+
+ brunit->curr_pre_targ >> br_ifid_reg->curr_pre_targ_in;
+ brunit->curr_pre_take >> br_ifid_reg->curr_pre_take_in;
+
+ br_ifid_reg->curr_pre_targ_out >> br_idex_reg->curr_pre_targ_in;
+ br_ifid_reg->curr_pre_take_out >> br_idex_reg->curr_pre_take_in;
+
+ idex_reg->pc_out >> brunit->prev_pc;
+ br_idex_reg->curr_pre_take_out >> brunit->prev_pre_take;
+
+ br_idex_reg->curr_pre_targ_out >> br_comp_target->op1;
+ alu->res >> br_comp_target->op2;
+
+ br_comp_target->out >> br_miss->curr_equal_targets;
+ branch->res >> br_miss->curr_act_take;
+ br_idex_reg->curr_pre_take_out >> br_miss->curr_pre_take;
+ br_idex_reg->curr_is_b_out >> br_miss->curr_is_b;
+ br_idex_reg->curr_is_j_out >> br_miss->curr_is_j;
+
+ br_miss->curr_miss_1 >> *br_miss_or->in[0];
+ br_miss->curr_miss_2 >> *br_miss_or->in[1];
+
+ br_miss_or->out >> brunit->prev_pre_miss;
+
+ br_idex_reg->curr_is_b_out >> brunit->prev_is_b;
+
+ brunit->curr_pre_targ >> br_nextpc->curr_pre_targ;
+ pc_4->out >> br_nextpc->pc_4_id;
+ idex_reg->pc4_out >> br_nextpc->pc_4_ex;
+ alu->res >> br_nextpc->curr_act_targ;
+ brunit->curr_pre_take >> br_nextpc->curr_pre_take;
+ br_miss->curr_miss_1 >> br_nextpc->curr_miss_1;
+ br_miss->curr_miss_2 >> br_nextpc->curr_miss_2;
+
+ br_miss_or->out >> *br_squash_not->in[0];
+
+ brunit->curr_is_b >> *br_if_b_and->in[0];
+ brunit->curr_is_j >> *br_if_j_and->in[0];
+ hzunit->hazardFEEnable >> *br_if_b_and->in[1];
+ hzunit->hazardFEEnable >> *br_if_j_and->in[1];
+ br_squash_not->out >> *br_if_b_and->in[2];
+ br_squash_not->out >> *br_if_j_and->in[2];
+ br_if_b_and->out >> br_ifid_reg->curr_is_b_in;
+ br_if_j_and->out >> br_ifid_reg->curr_is_j_in;
+
+ br_ifid_reg->curr_is_b_out >> *br_id_b_and->in[0];
+ br_ifid_reg->curr_is_j_out >> *br_id_j_and->in[0];
+ br_squash_not->out >> *br_id_b_and->in[1];
+ br_squash_not->out >> *br_id_j_and->in[1];
+ br_id_b_and->out >> br_idex_reg->curr_is_b_in;
+ br_id_j_and->out >> br_idex_reg->curr_is_j_in;
+
+ hzunit->hazardFEEnable >> *br_pc_or->in[0];
+ br_miss->curr_miss_1 >> *br_pc_or->in[1];
+ br_miss->curr_miss_2 >> *br_pc_or->in[2];
+
+ br_miss_or->out >> *ifid_reg_clear_or->in[0];
+ ifid_reg_clear_or->out >> ifid_reg->clear;
+ br_miss_or->out >> *idex_reg_clear_or->in[0];
+ idex_reg_clear_or->out >> idex_reg->clear;
+
+ efsc_or->out >> br_ifid_reg->clear;
+ efschz_or->out >> br_idex_reg->clear;
+
+ hzunit->hazardFEEnable >> br_ifid_reg->enable;
+ hzunit->hazardIDEXEnable >> br_idex_reg->enable;
+ }
+
+ // Design subcomponents
+ SUBCOMPONENT(registerFile, TYPE(RegisterFile));
+ SUBCOMPONENT(alu, TYPE(ALU));
+ SUBCOMPONENT(control, Control);
+ SUBCOMPONENT(immediate, TYPE(Immediate));
+ SUBCOMPONENT(decode, TYPE(Decode));
+ SUBCOMPONENT(branch, TYPE(Branch));
+ SUBCOMPONENT(pc_4, Adder);
+ SUBCOMPONENT(uncompress, TYPE(Uncompress));
+
+ // Registers
+ SUBCOMPONENT(pc_reg, RegisterClEn);
+
+ // Stage seperating registers
+ SUBCOMPONENT(ifid_reg, TYPE(IFID));
+ SUBCOMPONENT(idex_reg, TYPE(RV5S_IDEX));
+ SUBCOMPONENT(exmem_reg, TYPE(RV5S_EXMEM));
+ SUBCOMPONENT(memwb_reg, TYPE(RV5S_MEMWB));
+
+ // Multiplexers
+ SUBCOMPONENT(reg_wr_src, TYPE(EnumMultiplexer));
+ SUBCOMPONENT(alu_op1_src, TYPE(EnumMultiplexer));
+ SUBCOMPONENT(alu_op2_src, TYPE(EnumMultiplexer));
+ SUBCOMPONENT(reg1_fw_src, TYPE(EnumMultiplexer));
+ SUBCOMPONENT(reg2_fw_src, TYPE(EnumMultiplexer));
+ SUBCOMPONENT(pc_inc, TYPE(EnumMultiplexer));
+
+ // Memories
+ SUBCOMPONENT(instr_mem, TYPE(ROM));
+ SUBCOMPONENT(data_mem, TYPE(RVMemory));
+
+ // Forwarding & hazard detection units
+ SUBCOMPONENT(funit, ForwardingUnit);
+ SUBCOMPONENT(hzunit, HazardUnit);
+
+ // Branch prediction unit and necessary gates/registers
+ SUBCOMPONENT(brunit, TYPE(BranchUnit));
+
+ SUBCOMPONENT(br_ifid_reg, TYPE(RV5S_BR_IFID));
+ SUBCOMPONENT(br_idex_reg, TYPE(RV5S_BR_IDEX));
+
+ SUBCOMPONENT(br_comp_target, Eq);
+
+ SUBCOMPONENT(br_miss, BranchMiss);
+
+ SUBCOMPONENT(br_miss_or, TYPE(Or<1, 2>));
+ SUBCOMPONENT(br_if_b_and, TYPE(And<1, 3>));
+ SUBCOMPONENT(br_if_j_and, TYPE(And<1, 3>));
+ SUBCOMPONENT(br_id_b_and, TYPE(And<1, 2>));
+ SUBCOMPONENT(br_id_j_and, TYPE(And<1, 2>));
+ SUBCOMPONENT(br_squash_not, TYPE(Not<1, 1>));
+ SUBCOMPONENT(br_pc_or, TYPE(Or<1, 3>));
+
+ SUBCOMPONENT(br_nextpc, BranchNextPC);
+
+ SUBCOMPONENT(ifid_reg_clear_or, TYPE(Or<1, 2>));
+ SUBCOMPONENT(idex_reg_clear_or, TYPE(Or<1, 2>));
+
+ // Gates
+ // True if controlflow action or performing syscall finishing
+ SUBCOMPONENT(efsc_or, TYPE(Or<1, 2>));
+ // True if above or stalling due to load-use hazard
+ SUBCOMPONENT(efschz_or, TYPE(Or<1, 2>));
+
+ SUBCOMPONENT(mem_stalled_or, TYPE(Or<1, 2>));
+
+ // Address spaces
+ ADDRESSSPACEMM(m_memory);
+ ADDRESSSPACE(m_regMem);
+
+ SUBCOMPONENT(ecallChecker, EcallChecker);
+
+ // Ripes interface compliance
+ const ProcessorStructure &structure() const override { return m_structure; }
+ unsigned int getPcForStage(StageIndex idx) const override {
+ // clang-format off
+ switch (idx.index()) {
+ case IF: return pc_reg->out.uValue();
+ case ID: return ifid_reg->pc_out.uValue();
+ case EX: return idex_reg->pc_out.uValue();
+ case MEM: return exmem_reg->pc_out.uValue();
+ case WB: return memwb_reg->pc_out.uValue();
+ default: assert(false && "Processor does not contain stage");
+ }
+ Q_UNREACHABLE();
+ // clang-format on
+ }
+ AInt nextFetchedAddress() const override {
+ return br_nextpc->curr_next.uValue();
+ }
+ QString stageName(StageIndex idx) const override {
+ // clang-format off
+ switch (idx.index()) {
+ case IF: return "IF";
+ case ID: return "ID";
+ case EX: return "EX";
+ case MEM: return "MEM";
+ case WB: return "WB";
+ default: assert(false && "Processor does not contain stage");
+ }
+ Q_UNREACHABLE();
+ // clang-format on
+ }
+ StageInfo stageInfo(StageIndex stage) const override {
+ bool stageValid = true;
+ // Has the pipeline stage been filled?
+ stageValid &= stage.index() <= m_cycleCount;
+
+ // clang-format off
+ // Has the stage been cleared?
+ switch(stage.index()){
+ case ID: stageValid &= ifid_reg->valid_out.uValue(); break;
+ case EX: stageValid &= idex_reg->valid_out.uValue(); break;
+ case MEM: stageValid &= exmem_reg->valid_out.uValue(); break;
+ case WB: stageValid &= memwb_reg->valid_out.uValue(); break;
+ default: case IF: break;
+ }
+
+ // Is the stage carrying a valid (executable) PC?
+ switch(stage.index()){
+ case ID: stageValid &= isExecutableAddress(ifid_reg->pc_out.uValue()); break;
+ case EX: stageValid &= isExecutableAddress(idex_reg->pc_out.uValue()); break;
+ case MEM: stageValid &= isExecutableAddress(exmem_reg->pc_out.uValue()); break;
+ case WB: stageValid &= isExecutableAddress(memwb_reg->pc_out.uValue()); break;
+ default: case IF: stageValid &= isExecutableAddress(pc_reg->out.uValue()); break;
+ }
+
+ // Are we currently clearing the pipeline due to a syscall exit? if such, all stages before the EX stage are invalid
+ if(stage.index() < EX){
+ stageValid &= !ecallChecker->isSysCallExiting();
+ }
+ // clang-format on
+
+ // Gather stage state info
+ StageInfo::State state = StageInfo ::State::None;
+ switch (stage.index()) {
+ case IF:
+ break;
+ case ID:
+ if (m_cycleCount > ID && ifid_reg->valid_out.uValue() == 0) {
+ state = StageInfo::State::Flushed;
+ }
+ break;
+ case EX: {
+ if (idex_reg->stalled_out.uValue() == 1) {
+ state = StageInfo::State::Stalled;
+ } else if (m_cycleCount > EX && idex_reg->valid_out.uValue() == 0) {
+ state = StageInfo::State::Flushed;
+ }
+ break;
+ }
+ case MEM: {
+ if (exmem_reg->stalled_out.uValue() == 1) {
+ state = StageInfo::State::Stalled;
+ } else if (m_cycleCount > MEM && exmem_reg->valid_out.uValue() == 0) {
+ state = StageInfo::State::Flushed;
+ }
+ break;
+ }
+ case WB: {
+ if (memwb_reg->stalled_out.uValue() == 1) {
+ state = StageInfo::State::Stalled;
+ } else if (m_cycleCount > WB && memwb_reg->valid_out.uValue() == 0) {
+ state = StageInfo::State::Flushed;
+ }
+ break;
+ }
+ }
+
+ return StageInfo({getPcForStage(stage), stageValid, state});
+ }
+
+ void setProgramCounter(AInt address) override {
+ pc_reg->forceValue(0, address);
+ propagateDesign();
+ }
+ void setPCInitialValue(AInt address) override {
+ pc_reg->setInitValue(address);
+ }
+ AddressSpaceMM &getMemory() override { return *m_memory; }
+ VInt getRegister(RegisterFileType, unsigned i) const override {
+ return registerFile->getRegister(i);
+ }
+ void finalize(FinalizeReason fr) override {
+ if ((fr & FinalizeReason::exitSyscall) &&
+ !ecallChecker->isSysCallExiting()) {
+ // An exit system call was executed. Record the cycle of the execution,
+ // and enable the ecallChecker's system call exiting signal.
+ m_syscallExitCycle = m_cycleCount;
+ }
+ ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() ||
+ (fr & FinalizeReason::exitSyscall));
+ }
+ const std::vector breakpointTriggeringStages() const override {
+ return {{0, IF}};
+ }
+
+ MemoryAccess dataMemAccess() const override {
+ return memToAccessInfo(data_mem);
+ }
+ MemoryAccess instrMemAccess() const override {
+ auto instrAccess = memToAccessInfo(instr_mem);
+ instrAccess.type = MemoryAccess::Read;
+ return instrAccess;
+ }
+
+ bool finished() const override {
+ // The processor is finished when there are no more valid instructions in
+ // the pipeline
+ bool allStagesInvalid = true;
+ for (int stage = IF; stage < STAGECOUNT; stage++) {
+ allStagesInvalid &= !stageInfo({0, stage}).stage_valid;
+ if (!allStagesInvalid)
+ break;
+ }
+ return allStagesInvalid;
+ }
+
+ void setRegister(RegisterFileType, unsigned i, VInt v) override {
+ setSynchronousValue(registerFile->_wr_mem, i, v);
+ }
+
+ void clockProcessor() override {
+ // An instruction has been retired if the instruction in the WB stage is
+ // valid and the PC is within the executable range of the program
+ if (memwb_reg->valid_out.uValue() != 0 &&
+ isExecutableAddress(memwb_reg->pc_out.uValue())) {
+ m_instructionsRetired++;
+ }
+
+ if (brunit->prev_is_b.uValue()) {
+ PredictorHandler::getPredictor()->num_conditional++;
+ if (brunit->prev_pre_miss.uValue()) {
+ PredictorHandler::getPredictor()->num_conditional_miss++;
+ }
+ }
+
+ PredictorHandler::clock();
+
+ Design::clock();
+ }
+
+ void reverse() override {
+ if (m_syscallExitCycle != -1 && m_cycleCount == m_syscallExitCycle) {
+ // We are about to undo an exit syscall instruction. In this case, the
+ // syscall exiting sequence should be terminate
+ ecallChecker->setSysCallExiting(false);
+ m_syscallExitCycle = -1;
+ }
+
+ Design::reverse();
+
+ if (memwb_reg->valid_out.uValue() != 0 &&
+ isExecutableAddress(memwb_reg->pc_out.uValue())) {
+ m_instructionsRetired--;
+ }
+
+ if (brunit->prev_is_b.uValue()) {
+ PredictorHandler::getPredictor()->num_conditional--;
+ if (brunit->prev_pre_miss.uValue()) {
+ PredictorHandler::getPredictor()->num_conditional_miss--;
+ }
+ }
+
+ PredictorHandler::reverse();
+ }
+
+ void reset() override {
+ ecallChecker->setSysCallExiting(false);
+ Design::reset();
+ m_syscallExitCycle = -1;
+ PredictorHandler::getPredictor()->resetPredictorCounters();
+ }
+
+ static ProcessorISAInfo supportsISA() {
+ return ProcessorISAInfo{
+ std::make_shared()>>(QStringList()),
+ {"M", "C"},
+ {"M"}};
+ }
+ const ISAInfoBase *implementsISA() const override {
+ return m_enabledISA.get();
+ }
+
+ const std::set registerFiles() const override {
+ std::set rfs;
+ rfs.insert(RegisterFileType::GPR);
+
+ if (implementsISA()->extensionEnabled("F")) {
+ rfs.insert(RegisterFileType::FPR);
+ }
+ return rfs;
+ }
+
+ bool supportsBranchPrediction() const override { return true; }
+
+ // Branch Prediction
+
+ bool currentInstructionIsBranch() override {
+ unsigned opcode = uncompress->exp_instr.uValue() & 0x7F;
+ switch (opcode) {
+ case RVISA::Opcode::JAL:
+ case RVISA::Opcode::JALR:
+ case RVISA::Opcode::BRANCH:
+ return true;
+ default:
+ return false;
+ }
+ }
+
+ bool currentInstructionIsConditional() override {
+ unsigned opcode = uncompress->exp_instr.uValue() & 0x7F;
+ return opcode == RVISA::Opcode::BRANCH;
+ }
+
+ VInt currentInstructionImmediate() override {
+ unsigned opcode = uncompress->exp_instr.uValue() & 0x7F;
+ switch (opcode) {
+ case RVISA::Opcode::JAL: {
+ const auto fields = RVInstrParser::getParser()->decodeJ32Instr(
+ uncompress->exp_instr.uValue());
+ return VT_U(signextend<21>(fields[0] << 20 | fields[1] << 1 |
+ fields[2] << 11 | fields[3] << 12));
+ }
+ case RVISA::Opcode::JALR: {
+ return VT_U(signextend<12>((uncompress->exp_instr.uValue() >> 20)));
+ }
+ case RVISA::Opcode::BRANCH: {
+ const auto fields = RVInstrParser::getParser()->decodeB32Instr(
+ uncompress->exp_instr.uValue());
+ return VT_U(signextend<13>((fields[0] << 12) | (fields[1] << 5) |
+ (fields[5] << 1) | (fields[6] << 11)));
+ }
+ default:
+ return 0;
+ }
+ }
+
+ AInt currentInstructionTarget() override {
+ if (!currentInstructionIsBranch()) {
+ return 0;
+ }
+ return pc_reg->out.uValue() + currentInstructionImmediate();
+ }
+
+ bool currentGetPrediction() override {
+ return brunit->curr_pre_take.uValue();
+ }
+
+private:
+ /**
+ * @brief m_syscallExitCycle
+ * The variable will contain the cycle of which an exit system call was
+ * executed. From this, we may determine when we roll back an exit system call
+ * during rewinding.
+ */
+ long long m_syscallExitCycle = -1;
+ std::shared_ptr m_enabledISA;
+ ProcessorStructure m_structure = {{0, 5}};
+};
+
+} // namespace core
+} // namespace vsrtl
diff --git a/src/processors/RISC-V/rv5s_br/rv5s_br_extended_layout.json b/src/processors/RISC-V/rv5s_br/rv5s_br_extended_layout.json
new file mode 100644
index 000000000..304e8a95d
--- /dev/null
+++ b/src/processors/RISC-V/rv5s_br/rv5s_br_extended_layout.json
@@ -0,0 +1,36519 @@
+{
+ "m_layoutVersion": 1,
+ "ComponentGraphic": {
+ "Top name": "5-Stage RISC-V Processor",
+ "Expanded": true,
+ "Rect": {
+ "x": 0,
+ "y": 0,
+ "w": 140,
+ "h": 83
+ },
+ "rot": 0,
+ "Component border": [],
+ "alu": {
+ "Top name": "alu",
+ "Rect": {
+ "x": 0,
+ "y": 0,
+ "w": 9,
+ "h": 12
+ },
+ "rot": 0,
+ "Pos": {
+ "x": 1288,
+ "y": 350
+ },
+ "Visible": true,
+ "User hidden": false,
+ "Component border": [
+ {
+ "key": 0,
+ "value": [
+ {
+ "key": "op1",
+ "value": 3
+ },
+ {
+ "key": "op2",
+ "value": 10
+ }
+ ]
+ },
+ {
+ "key": 1,
+ "value": [
+ {
+ "key": "res",
+ "value": 6
+ }
+ ]
+ },
+ {
+ "key": 2,
+ "value": [
+ {
+ "key": "ctrl",
+ "value": 1
+ }
+ ]
+ }
+ ],
+ "ctrl": {
+ "Label": {
+ "Visible": true,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 8,
+ "Text": {
+ "str": "ctrl"
+ },
+ "Pos": {
+ "x": 2.6751872429254037,
+ "y": 3.3065709124909405
+ },
+ "Alignment": 132
+ },
+ "ValueLabel": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "NOP"
+ },
+ "Pos": {
+ "x": 1305.0,
+ "y": 344.0
+ },
+ "Alignment": 132
+ },
+ "UserHidden": false,
+ "PortWidthVisible": true
+ },
+ "op1": {
+ "Label": {
+ "Visible": true,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "Op 1"
+ },
+ "Pos": {
+ "x": 3.246290471462544,
+ "y": 31.16263376087386
+ },
+ "Alignment": 132
+ },
+ "ValueLabel": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "0x0000000000000000"
+ },
+ "Pos": {
+ "x": 1291.0,
+ "y": 386.0
+ },
+ "Alignment": 132
+ },
+ "UserHidden": false,
+ "PortWidthVisible": true
+ },
+ "op2": {
+ "Label": {
+ "Visible": true,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "Op 2"
+ },
+ "Pos": {
+ "x": 2.3038449197999855,
+ "y": 126.22906543428258
+ },
+ "Alignment": 132
+ },
+ "ValueLabel": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "0x0000000000000000"
+ },
+ "Pos": {
+ "x": 1291.0,
+ "y": 484.0
+ },
+ "Alignment": 132
+ },
+ "UserHidden": false,
+ "PortWidthVisible": true
+ },
+ "res": {
+ "Label": {
+ "Visible": true,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "Res"
+ },
+ "Pos": {
+ "x": 97.44508153550783,
+ "y": 71.87880124802587
+ },
+ "Alignment": 132
+ },
+ "ValueLabel": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "0x00000000deadbeef"
+ },
+ "Pos": {
+ "x": 1417.0,
+ "y": 428.0
+ },
+ "Alignment": 132
+ },
+ "UserHidden": false,
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+ "Italic": false,
+ "PtSize": 8,
+ "Text": {
+ "str": "wr_width"
+ },
+ "Pos": {
+ "x": 28.0,
+ "y": 42.0
+ },
+ "Alignment": 132
+ },
+ "ValueLabel": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "-8"
+ },
+ "Pos": {
+ "x": 124.6375,
+ "y": 88.8
+ },
+ "Alignment": 132
+ },
+ "UserHidden": false,
+ "PortWidthVisible": false
+ },
+ "Name label": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 12,
+ "Text": {
+ "str": "_wr_mem"
+ },
+ "Pos": {
+ "x": 21.0,
+ "y": -19.0
+ },
+ "Alignment": 132
+ },
+ "Indicators": []
+ },
+ "wr_en_0": {
+ "Top name": "wr_en_0",
+ "Rect": {
+ "x": 0,
+ "y": 0,
+ "w": 2,
+ "h": 2
+ },
+ "rot": 0,
+ "Pos": {
+ "x": 42,
+ "y": 84
+ },
+ "Visible": false,
+ "User hidden": false,
+ "Component border": [
+ {
+ "key": 1,
+ "value": [
+ {
+ "key": "out",
+ "value": 1
+ }
+ ]
+ }
+ ],
+ "out": {
+ "Label": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 8,
+ "Text": {
+ "str": "out"
+ },
+ "Pos": {
+ "x": 28.0,
+ "y": 14.0
+ },
+ "Alignment": 132
+ },
+ "ValueLabel": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "0x0"
+ },
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+ "x": 73.0,
+ "y": 92.0
+ },
+ "Alignment": 132
+ },
+ "UserHidden": false,
+ "PortWidthVisible": false
+ },
+ "out_out_wire": {
+ "Parent": "registerFile",
+ "From port": {
+ "first": 0,
+ "second": [
+ "out",
+ "wr_en_0"
+ ]
+ },
+ "To ports": [
+ {
+ "key": 1,
+ "value": [
+ "wr_en",
+ "_wr_mem"
+ ]
+ }
+ ],
+ "points": [
+ {
+ "key": 2,
+ "value": {
+ "x": 112,
+ "y": 70
+ }
+ },
+ {
+ "key": 3,
+ "value": {
+ "x": 112,
+ "y": 224
+ }
+ }
+ ],
+ "wires": [
+ {
+ "first": 2,
+ "second": 1
+ },
+ {
+ "first": 0,
+ "second": 3
+ },
+ {
+ "first": 3,
+ "second": 2
+ }
+ ]
+ },
+ "Name label": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 12,
+ "Text": {
+ "str": "wr_en_0"
+ },
+ "Pos": {
+ "x": 14.0,
+ "y": -19.0
+ },
+ "Alignment": 132
+ },
+ "Indicators": []
+ },
+ "r1_out_out_wire": {
+ "Parent": "5-Stage RISC-V Processor",
+ "From port": {
+ "first": 0,
+ "second": [
+ "r1_out",
+ "registerFile"
+ ]
+ },
+ "To ports": [
+ {
+ "key": 1,
+ "value": [
+ "r1_in",
+ "idex_reg"
+ ]
+ }
+ ],
+ "points": [],
+ "wires": [
+ {
+ "first": 0,
+ "second": 1
+ }
+ ]
+ },
+ "r2_out_out_wire": {
+ "Parent": "5-Stage RISC-V Processor",
+ "From port": {
+ "first": 0,
+ "second": [
+ "r2_out",
+ "registerFile"
+ ]
+ },
+ "To ports": [
+ {
+ "key": 1,
+ "value": [
+ "r2_in",
+ "idex_reg"
+ ]
+ }
+ ],
+ "points": [],
+ "wires": [
+ {
+ "first": 0,
+ "second": 1
+ }
+ ]
+ },
+ "Name label": {
+ "Visible": true,
+ "Bold": true,
+ "Italic": false,
+ "PtSize": 12,
+ "Text": {
+ "str": "Registers"
+ },
+ "Pos": {
+ "x": 35.440362932129577,
+ "y": 41.782244669880217
+ },
+ "Alignment": 132
+ },
+ "Indicators": [
+ "wr_en"
+ ]
+ },
+ "uncompress": {
+ "Top name": "uncompress",
+ "Rect": {
+ "x": 0,
+ "y": 0,
+ "w": 6,
+ "h": 3
+ },
+ "rot": 0,
+ "Pos": {
+ "x": 238,
+ "y": 490
+ },
+ "Visible": true,
+ "User hidden": false,
+ "Component border": [
+ {
+ "key": 0,
+ "value": [
+ {
+ "key": "Pc_Inc",
+ "value": 1
+ }
+ ]
+ },
+ {
+ "key": 1,
+ "value": [
+ {
+ "key": "exp_instr",
+ "value": 2
+ }
+ ]
+ },
+ {
+ "key": 2,
+ "value": [
+ {
+ "key": "instr",
+ "value": 3
+ }
+ ]
+ }
+ ],
+ "instr": {
+ "Label": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 8,
+ "Text": {
+ "str": "instr"
+ },
+ "Pos": {
+ "x": 24.649289875701073,
+ "y": 8.675355062149379
+ },
+ "Alignment": 132
+ },
+ "ValueLabel": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "0x0000006f"
+ },
+ "Pos": {
+ "x": 280.0,
+ "y": 490.0
+ },
+ "Alignment": 132
+ },
+ "UserHidden": false,
+ "PortWidthVisible": false
+ },
+ "Pc_Inc": {
+ "Label": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 8,
+ "Text": {
+ "str": "Pc_Inc"
+ },
+ "Pos": {
+ "x": 0.0,
+ "y": 14.0
+ },
+ "Alignment": 132
+ },
+ "ValueLabel": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "0x1"
+ },
+ "Pos": {
+ "x": 238.0,
+ "y": 504.0
+ },
+ "Alignment": 132
+ },
+ "UserHidden": false,
+ "PortWidthVisible": true
+ },
+ "exp_instr": {
+ "Label": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 8,
+ "Text": {
+ "str": "exp_instr"
+ },
+ "Pos": {
+ "x": 112.0,
+ "y": 28.0
+ },
+ "Alignment": 132
+ },
+ "ValueLabel": {
+ "Visible": false,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "0x0000006f"
+ },
+ "Pos": {
+ "x": 350.0,
+ "y": 518.0
+ },
+ "Alignment": 132
+ },
+ "UserHidden": false,
+ "PortWidthVisible": true
+ },
+ "Pc_Inc_out_wire": {
+ "Parent": "5-Stage RISC-V Processor",
+ "From port": {
+ "first": 0,
+ "second": [
+ "Pc_Inc",
+ "uncompress"
+ ]
+ },
+ "To ports": [
+ {
+ "key": 1,
+ "value": [
+ "select",
+ "pc_inc"
+ ]
+ }
+ ],
+ "points": [
+ {
+ "key": 2,
+ "value": {
+ "x": 154,
+ "y": 504
+ }
+ },
+ {
+ "key": 3,
+ "value": {
+ "x": 154,
+ "y": 350
+ }
+ }
+ ],
+ "wires": [
+ {
+ "first": 0,
+ "second": 2
+ },
+ {
+ "first": 3,
+ "second": 1
+ },
+ {
+ "first": 2,
+ "second": 3
+ }
+ ]
+ },
+ "exp_instr_out_wire": {
+ "Parent": "5-Stage RISC-V Processor",
+ "From port": {
+ "first": 0,
+ "second": [
+ "exp_instr",
+ "uncompress"
+ ]
+ },
+ "To ports": [
+ {
+ "key": 1,
+ "value": [
+ "instr_in",
+ "ifid_reg"
+ ]
+ }
+ ],
+ "points": [
+ {
+ "key": 2,
+ "value": {
+ "x": 364,
+ "y": 518
+ }
+ },
+ {
+ "key": 3,
+ "value": {
+ "x": 364,
+ "y": 518
+ }
+ }
+ ],
+ "wires": [
+ {
+ "first": 0,
+ "second": 3
+ },
+ {
+ "first": 2,
+ "second": 1
+ },
+ {
+ "first": 3,
+ "second": 2
+ }
+ ]
+ },
+ "Name label": {
+ "Visible": true,
+ "Bold": true,
+ "Italic": false,
+ "PtSize": 10,
+ "Text": {
+ "str": "Compressed\ndecoder"
+ },
+ "Pos": {
+ "x": 1.4647727129833186,
+ "y": -0.047240688738256157
+ },
+ "Alignment": 132
+ },
+ "Indicators": []
+ },
+ "Name label": {
+ "Visible": true,
+ "Bold": false,
+ "Italic": false,
+ "PtSize": 18,
+ "Text": {
+ "str": "5-Stage RISC-V Processor w/ Branch Prediction"
+ },
+ "Pos": {
+ "x": 747.3769956439079,
+ "y": -46.91297605451626
+ },
+ "Alignment": 132
+ },
+ "Indicators": []
+ }
+}
\ No newline at end of file
diff --git a/src/processors/RISC-V/rv5s_br/rv5s_branch_miss.h b/src/processors/RISC-V/rv5s_br/rv5s_branch_miss.h
new file mode 100644
index 000000000..c8c496db9
--- /dev/null
+++ b/src/processors/RISC-V/rv5s_br/rv5s_branch_miss.h
@@ -0,0 +1,40 @@
+#pragma once
+
+#include "../riscv.h"
+
+#include "VSRTL/core/vsrtl_component.h"
+
+namespace vsrtl {
+namespace core {
+using namespace Ripes;
+
+class BranchMiss : public Component {
+public:
+ BranchMiss(const std::string &name, SimComponent *parent)
+ : Component(name, parent) {
+ curr_miss_1 << [=] {
+ return (curr_is_j.uValue() && !curr_equal_targets.uValue()) |
+ (!curr_pre_take.uValue() && curr_act_take.uValue() &&
+ curr_is_b.uValue()) |
+ (curr_pre_take.uValue() && curr_act_take.uValue() &&
+ !curr_equal_targets.uValue() && curr_is_b.uValue());
+ };
+
+ curr_miss_2 << [=] {
+ return (!curr_act_take.uValue() && curr_pre_take.uValue() &&
+ curr_is_b.uValue());
+ };
+ }
+
+ INPUTPORT(curr_equal_targets, 1);
+ INPUTPORT(curr_act_take, 1);
+ INPUTPORT(curr_pre_take, 1);
+ INPUTPORT(curr_is_b, 1);
+ INPUTPORT(curr_is_j, 1);
+ OUTPUTPORT(curr_miss_1, 1);
+ OUTPUTPORT(curr_miss_2, 1);
+
+private:
+};
+} // namespace core
+} // namespace vsrtl
\ No newline at end of file
diff --git a/src/processors/RISC-V/rv5s_br/rv5s_branch_nextpc.h b/src/processors/RISC-V/rv5s_br/rv5s_branch_nextpc.h
new file mode 100644
index 000000000..820570739
--- /dev/null
+++ b/src/processors/RISC-V/rv5s_br/rv5s_branch_nextpc.h
@@ -0,0 +1,41 @@
+#pragma once
+
+#include "../riscv.h"
+
+#include "VSRTL/core/vsrtl_component.h"
+
+namespace vsrtl {
+namespace core {
+using namespace Ripes;
+
+template
+class BranchNextPC : public Component {
+public:
+ BranchNextPC(const std::string &name, SimComponent *parent)
+ : Component(name, parent) {
+ curr_next << [=] {
+ if (curr_miss_1.uValue()) {
+ return curr_act_targ.uValue();
+ } else if (curr_miss_2.uValue()) {
+ return pc_4_ex.uValue();
+ } else if (curr_pre_take.uValue()) {
+ return curr_pre_targ.uValue();
+ } else {
+ return pc_4_id.uValue();
+ }
+ };
+ }
+
+ INPUTPORT(curr_pre_targ, XLEN);
+ INPUTPORT(pc_4_id, XLEN);
+ INPUTPORT(pc_4_ex, XLEN);
+ INPUTPORT(curr_act_targ, XLEN);
+ INPUTPORT(curr_pre_take, 1);
+ INPUTPORT(curr_miss_1, 1);
+ INPUTPORT(curr_miss_2, 1);
+ OUTPUTPORT(curr_next, XLEN);
+
+private:
+};
+} // namespace core
+} // namespace vsrtl
\ No newline at end of file
diff --git a/src/processors/RISC-V/rv5s_br/rv5s_branch_regs.h b/src/processors/RISC-V/rv5s_br/rv5s_branch_regs.h
new file mode 100644
index 000000000..70d3abac8
--- /dev/null
+++ b/src/processors/RISC-V/rv5s_br/rv5s_branch_regs.h
@@ -0,0 +1,57 @@
+#pragma once
+
+#include "../riscv.h"
+
+#include "VSRTL/core/vsrtl_component.h"
+#include "VSRTL/core/vsrtl_register.h"
+
+namespace vsrtl {
+namespace core {
+using namespace Ripes;
+
+template
+class RV5S_BR_IFID : public Component {
+public:
+ RV5S_BR_IFID(const std::string &name, SimComponent *parent)
+ : Component(name, parent) {
+ CONNECT_REGISTERED_CLEN_INPUT(curr_pre_targ, clear, enable);
+ CONNECT_REGISTERED_CLEN_INPUT(curr_pre_take, clear, enable);
+ CONNECT_REGISTERED_CLEN_INPUT(curr_is_b, clear, enable);
+ CONNECT_REGISTERED_CLEN_INPUT(curr_is_j, clear, enable);
+ }
+
+ // Data
+ REGISTERED_CLEN_INPUT(curr_pre_targ, XLEN);
+ REGISTERED_CLEN_INPUT(curr_pre_take, 1);
+ REGISTERED_CLEN_INPUT(curr_is_b, 1);
+ REGISTERED_CLEN_INPUT(curr_is_j, 1);
+
+ // Register bank controls
+ INPUTPORT(enable, 1);
+ INPUTPORT(clear, 1);
+};
+
+template
+class RV5S_BR_IDEX : public Component {
+public:
+ RV5S_BR_IDEX(const std::string &name, SimComponent *parent)
+ : Component(name, parent) {
+ CONNECT_REGISTERED_CLEN_INPUT(curr_pre_targ, clear, enable);
+ CONNECT_REGISTERED_CLEN_INPUT(curr_pre_take, clear, enable);
+ CONNECT_REGISTERED_CLEN_INPUT(curr_is_b, clear, enable);
+ CONNECT_REGISTERED_CLEN_INPUT(curr_is_j, clear, enable);
+ }
+
+ // Data
+ REGISTERED_CLEN_INPUT(curr_pre_targ, XLEN);
+ REGISTERED_CLEN_INPUT(curr_pre_take, 1);
+ REGISTERED_CLEN_INPUT(curr_is_b, 1);
+ REGISTERED_CLEN_INPUT(curr_is_j, 1);
+
+ // Register bank controls
+ INPUTPORT(enable, 1);
+ INPUTPORT(clear, 1);
+};
+
+} // namespace core
+} // namespace vsrtl
diff --git a/src/processors/RISC-V/rv5s_br/rv5s_branchunit.h b/src/processors/RISC-V/rv5s_br/rv5s_branchunit.h
new file mode 100644
index 000000000..eb7072cfe
--- /dev/null
+++ b/src/processors/RISC-V/rv5s_br/rv5s_branchunit.h
@@ -0,0 +1,68 @@
+#pragma once
+
+#include "../riscv.h"
+
+#include "VSRTL/core/vsrtl_component.h"
+#include "VSRTL/core/vsrtl_register.h"
+
+#include "../../../processorhandler.h"
+#include "../../branch/branchpredictionprocessor.h"
+#include "../../branch/predictorhandler.h"
+#include "../rv_decode.h"
+#include "../rv_immediate.h"
+
+#include
+
+namespace vsrtl {
+namespace core {
+using namespace Ripes;
+
+template
+class BranchUnit : public Component {
+public:
+ BranchUnit(const std::string &name, SimComponent *parent)
+ : Component(name, parent) {
+ PredictorHandler::changePredictor(0, 8, 8, 2);
+
+ curr_pre_targ << [=] { return get_curr_pre_targ(); };
+
+ curr_pre_take << [=] {
+ PredictorHandler::getPredictor()->updatePrediction(
+ prev_pc.uValue(), prev_pre_take.uValue(), prev_pre_miss.uValue(),
+ prev_is_b.uValue(), prev_is_b.uValue());
+ bool take = PredictorHandler::getPredictor()->getPrediction(
+ curr_pc.uValue(), get_curr_is_b() || get_curr_is_j(),
+ get_curr_is_b());
+ return take;
+ };
+
+ curr_is_b << [=] { return get_curr_is_b(); };
+
+ curr_is_j << [=] { return get_curr_is_j(); };
+ }
+
+ INPUTPORT(prev_is_b, 1);
+ INPUTPORT(prev_pc, XLEN);
+ INPUTPORT(prev_pre_take, 1);
+ INPUTPORT(prev_pre_miss, 1);
+ INPUTPORT(curr_pc, XLEN);
+ OUTPUTPORT(curr_pre_targ, XLEN);
+ OUTPUTPORT(curr_pre_take, 1);
+ OUTPUTPORT(curr_is_b, 1);
+ OUTPUTPORT(curr_is_j, 1);
+
+ void setProc(BranchPredictionProcessor *p) { this->proc = p; }
+
+private:
+ BranchPredictionProcessor *proc = nullptr;
+ AInt get_curr_pre_targ() { return proc->currentInstructionTarget(); }
+
+ bool get_curr_is_b() { return proc->currentInstructionIsConditional(); }
+
+ bool get_curr_is_j() {
+ return proc->currentInstructionIsBranch() &&
+ !proc->currentInstructionIsConditional();
+ }
+};
+} // namespace core
+} // namespace vsrtl
\ No newline at end of file
diff --git a/src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h b/src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
index 2fcb85870..fe70c8398 100644
--- a/src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
+++ b/src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
@@ -505,6 +505,8 @@ class RV5S_NO_FW : public RipesVSRTLProcessor {
return rfs;
}
+ bool supportsBranchPrediction() const override { return false; }
+
private:
/**
* @brief m_syscallExitCycle
diff --git a/src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h b/src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
index 304a95f75..db17bd6c5 100644
--- a/src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
+++ b/src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
@@ -455,6 +455,8 @@ class RV5S_NO_FW_HZ : public RipesVSRTLProcessor {
return rfs;
}
+ bool supportsBranchPrediction() const override { return false; }
+
private:
/**
* @brief m_syscallExitCycle
diff --git a/src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h b/src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
index afbf070e9..0f95c1c07 100644
--- a/src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
+++ b/src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
@@ -490,6 +490,8 @@ class RV5S_NO_HZ : public RipesVSRTLProcessor {
return rfs;
}
+ bool supportsBranchPrediction() const override { return false; }
+
private:
/**
* @brief m_syscallExitCycle
diff --git a/src/processors/RISC-V/rv6s_dual/rv6s_dual.h b/src/processors/RISC-V/rv6s_dual/rv6s_dual.h
index e59cec8f3..4244b4390 100644
--- a/src/processors/RISC-V/rv6s_dual/rv6s_dual.h
+++ b/src/processors/RISC-V/rv6s_dual/rv6s_dual.h
@@ -899,6 +899,8 @@ class RV6S_DUAL : public RipesVSRTLProcessor {
return rfs;
}
+ bool supportsBranchPrediction() const override { return false; }
+
private:
/**
* @brief m_syscallExitCycle
diff --git a/src/processors/RISC-V/rvss/rvss.h b/src/processors/RISC-V/rvss/rvss.h
index 39de30df6..0947ebd07 100644
--- a/src/processors/RISC-V/rvss/rvss.h
+++ b/src/processors/RISC-V/rvss/rvss.h
@@ -257,6 +257,8 @@ class RVSS : public RipesVSRTLProcessor {
return rfs;
}
+ bool supportsBranchPrediction() const override { return false; }
+
private:
bool m_finishInNextCycle = false;
bool m_finished = false;
diff --git a/src/processors/branch/branchpredictionprocessor.h b/src/processors/branch/branchpredictionprocessor.h
new file mode 100644
index 000000000..0cf0d66bd
--- /dev/null
+++ b/src/processors/branch/branchpredictionprocessor.h
@@ -0,0 +1,56 @@
+#pragma once
+
+#include "../../ripes_types.h"
+#include
+
+namespace Ripes {
+
+/**
+ * @brief The BranchPredictionProcessor class
+ * Interface for processors that support branch prediction.
+ *
+ * Inherited alongside the RipesVSRTLProcessor class
+ */
+class BranchPredictionProcessor {
+public:
+ BranchPredictionProcessor() {}
+ virtual ~BranchPredictionProcessor() {}
+
+ /**
+ * @brief currentInstructionIsBranch
+ *
+ * @return True if current instruction is any type of branch, false otherwise
+ */
+ virtual bool currentInstructionIsBranch() = 0;
+
+ /**
+ * @briefcurrentInstructionIsConditional
+ *
+ * @return True if current instruction is a conditional branch, false
+ * otherwise
+ */
+ virtual bool currentInstructionIsConditional() = 0;
+
+ /**
+ * @brief currentInstructionImmediate
+ *
+ * @return The value of the immediate for the current instruction
+ */
+ virtual VInt currentInstructionImmediate() = 0;
+
+ /**
+ * @brief currentInstructionTarget
+ *
+ * @return Gets the value of the current branch target
+ */
+ virtual AInt currentInstructionTarget() = 0;
+
+ /**
+ * @brief currentGetPrediction
+ *
+ * @return True if current instruction is predicted taken
+ */
+ virtual bool currentGetPrediction() = 0;
+};
+
+} // namespace Ripes
diff --git a/src/processors/branch/predictorhandler.h b/src/processors/branch/predictorhandler.h
new file mode 100644
index 000000000..0ea203191
--- /dev/null
+++ b/src/processors/branch/predictorhandler.h
@@ -0,0 +1,95 @@
+#pragma once
+
+#include
+
+#include "ripesbranchpredictor.h"
+
+#include "predictors/always_not_taken_predictor.h"
+#include "predictors/always_taken_predictor.h"
+#include "predictors/counter_predictor.h"
+#include "predictors/global_predictor.h"
+#include "predictors/local_predictor.h"
+
+#include "../../ripessettings.h"
+
+namespace Ripes {
+
+/**
+ * @brief The ProcessorHandler class
+ * Manages the branch predictor and provides an ISA and processor agnostic
+ * interface.
+ */
+class PredictorHandler : public QObject {
+
+public:
+ typedef uint64_t XLEN_T;
+ typedef uint16_t ARRAY_T;
+
+ PredictorHandler() {
+ connect(RipesSettings::getObserver(RIPES_SETTING_REWINDSTACKSIZE),
+ &SettingObserver::modified, this, [=](const auto &size) {
+ PredictorHandler::getPredictor()->setReverseStackSize(
+ size.toUInt());
+ });
+ }
+
+ // Returns a pointer to the PredictorHandler singleton.
+ static PredictorHandler *get() {
+ static auto *handler = new PredictorHandler;
+ return handler;
+ }
+
+ static RipesBranchPredictor *getPredictor() {
+ return get()->_getPredictor();
+ }
+
+ static void changePredictor(uint8_t predictor, uint16_t num_address_bits,
+ uint16_t num_history_bits,
+ uint16_t num_state_bits) {
+
+ get()->_changePredictor(predictor, num_address_bits, num_history_bits,
+ num_state_bits);
+ }
+
+ static void clock() { return get()->_clock(); }
+ static void reverse() { return get()->_reverse(); }
+
+private:
+ RipesBranchPredictor *_getPredictor() {
+ return this->current_predictor.get();
+ }
+
+ void _changePredictor(uint8_t predictor, uint16_t num_address_bits,
+ uint16_t num_history_bits, uint16_t num_state_bits) {
+ switch (predictor) {
+ case 0:
+ this->current_predictor.reset(new LocalPredictor(
+ num_address_bits, num_history_bits, num_state_bits));
+ break;
+ case 1:
+ this->current_predictor.reset(new GlobalPredictor(
+ num_history_bits, num_state_bits));
+ break;
+ case 2:
+ this->current_predictor.reset(
+ new CounterPredictor(num_state_bits));
+ break;
+ case 3:
+ this->current_predictor.reset(
+ new AlwaysTakenPredictor());
+ break;
+ case 4:
+ this->current_predictor.reset(
+ new AlwaysNotTakenPredictor());
+ break;
+ }
+ }
+
+ void _clock() { getPredictor()->saveState(); }
+
+ void _reverse() { getPredictor()->restoreState(); }
+
+ std::unique_ptr> current_predictor;
+};
+
+} // namespace Ripes
diff --git a/src/processors/branch/predictors/always_not_taken_predictor.h b/src/processors/branch/predictors/always_not_taken_predictor.h
new file mode 100644
index 000000000..2f489947f
--- /dev/null
+++ b/src/processors/branch/predictors/always_not_taken_predictor.h
@@ -0,0 +1,56 @@
+#pragma once
+
+#include "../ripesbranchpredictor.h"
+
+namespace Ripes {
+
+template
+class AlwaysNotTakenPredictor : public RipesBranchPredictor {
+ static_assert(std::is_same::value ||
+ std::is_same::value,
+ "Only supports 32- and 64-bit variants");
+ static constexpr unsigned XLEN = sizeof(XLEN_T) * 8;
+
+public:
+ AlwaysNotTakenPredictor() {
+ this->lht.reset(new ARRAY_T[1]);
+ this->pht.reset(new ARRAY_T[1]);
+ resetPredictorState();
+ }
+
+ bool getPrediction(XLEN_T addr, bool is_branch,
+ bool is_conditional) override {
+ Q_UNUSED(addr);
+ if (is_branch && !is_conditional) {
+ return true;
+ }
+
+ return false;
+ }
+
+ void updatePrediction(XLEN_T addr, bool predict_taken, bool miss,
+ bool is_branch, bool is_conditional) override {
+ Q_UNUSED(addr);
+ Q_UNUSED(predict_taken);
+ Q_UNUSED(miss);
+ Q_UNUSED(is_branch);
+ Q_UNUSED(is_conditional);
+ return;
+ }
+
+ void setReverseStackSize(VInt size) override {
+ Q_UNUSED(size);
+ return;
+ }
+
+ void saveState() override { return; }
+
+ void restoreState() override { return; }
+
+ void resetPredictorState() override {
+ this->lht.get()[0] = 0;
+ this->pht.get()[0] = 0;
+ }
+};
+
+} // namespace Ripes
\ No newline at end of file
diff --git a/src/processors/branch/predictors/always_taken_predictor.h b/src/processors/branch/predictors/always_taken_predictor.h
new file mode 100644
index 000000000..b76188341
--- /dev/null
+++ b/src/processors/branch/predictors/always_taken_predictor.h
@@ -0,0 +1,60 @@
+#pragma once
+
+#include "../ripesbranchpredictor.h"
+
+namespace Ripes {
+
+template
+class AlwaysTakenPredictor : public RipesBranchPredictor {
+ static_assert(std::is_same::value ||
+ std::is_same::value,
+ "Only supports 32- and 64-bit variants");
+ static constexpr unsigned XLEN = sizeof(XLEN_T) * 8;
+
+public:
+ AlwaysTakenPredictor() {
+ this->lht.reset(new ARRAY_T[1]);
+ this->pht.reset(new ARRAY_T[1]);
+ resetPredictorState();
+ }
+
+ bool getPrediction(XLEN_T addr, bool is_branch,
+ bool is_conditional) override {
+ Q_UNUSED(addr);
+ if (is_branch && !is_conditional) {
+ return true;
+ }
+
+ else if (!is_conditional) {
+ return false;
+ }
+
+ return true;
+ }
+
+ void updatePrediction(XLEN_T addr, bool predict_taken, bool miss,
+ bool is_branch, bool is_conditional) override {
+ Q_UNUSED(addr);
+ Q_UNUSED(predict_taken);
+ Q_UNUSED(miss);
+ Q_UNUSED(is_branch);
+ Q_UNUSED(is_conditional);
+ return;
+ }
+
+ void setReverseStackSize(VInt size) override {
+ Q_UNUSED(size);
+ return;
+ }
+
+ void saveState() override { return; }
+
+ void restoreState() override { return; }
+
+ void resetPredictorState() override {
+ this->lht.get()[0] = 0;
+ this->pht.get()[0] = 0;
+ }
+};
+
+} // namespace Ripes
\ No newline at end of file
diff --git a/src/processors/branch/predictors/counter_predictor.h b/src/processors/branch/predictors/counter_predictor.h
new file mode 100644
index 000000000..160f1be56
--- /dev/null
+++ b/src/processors/branch/predictors/counter_predictor.h
@@ -0,0 +1,102 @@
+#pragma once
+
+#include "../ripesbranchpredictor.h"
+
+namespace Ripes {
+
+template
+class CounterPredictor : public RipesBranchPredictor {
+ static_assert(std::is_same::value ||
+ std::is_same::value,
+ "Only supports 32- and 64-bit variants");
+ static constexpr unsigned XLEN = sizeof(XLEN_T) * 8;
+
+public:
+ CounterPredictor(VInt num_state_bits) {
+ this->num_state_bits = num_state_bits;
+ this->lht.reset(new ARRAY_T[1]);
+ this->pht.reset(new ARRAY_T[1]);
+ resetPredictorState();
+ }
+
+ VInt num_state_bits = 0;
+
+ bool getPrediction(XLEN_T addr, bool is_branch,
+ bool is_conditional) override {
+ Q_UNUSED(addr);
+ if (is_branch && !is_conditional) {
+ return true;
+ }
+
+ else if (!is_conditional) {
+ return false;
+ }
+
+ switch (this->pht.get()[0] >> (num_state_bits - 1)) {
+ case 0:
+ return false;
+ case 1:
+ return true;
+ default:
+ return false;
+ }
+ }
+
+ void updatePrediction(XLEN_T addr, bool predict_taken, bool miss,
+ bool is_branch, bool is_conditional) override {
+ Q_UNUSED(addr);
+ Q_UNUSED(is_branch);
+ if (!is_conditional) {
+ return;
+ }
+
+ bool prev_actual_taken = predict_taken ^ miss;
+
+ if (prev_actual_taken) {
+ if (this->pht.get()[0] == (1 << num_state_bits) - 1) {
+ return;
+ } else {
+ this->pht.get()[0] += 1;
+ }
+ } else {
+ if (this->pht.get()[0] == 0) {
+ return;
+ } else {
+ this->pht.get()[0] -= 1;
+ }
+ }
+ }
+
+ void setReverseStackSize(VInt size) override {
+ if (this->rev_stack_max_size > size) {
+ m_rev_state_stack.resize(size);
+ }
+ }
+
+ void saveState() override {
+ m_rev_state_stack.push_front(this->pht.get()[0]);
+
+ if (m_rev_state_stack.size() > this->rev_stack_max_size) {
+ m_rev_state_stack.pop_back();
+ }
+ }
+
+ void restoreState() override {
+ if (m_rev_state_stack.size() == 0) {
+ return;
+ }
+
+ this->pht.get()[0] = m_rev_state_stack.front();
+ m_rev_state_stack.pop_front();
+ }
+
+ void resetPredictorState() override {
+ this->lht.get()[0] = 0;
+ this->pht.get()[0] = 0;
+ }
+
+private:
+ std::deque m_rev_state_stack;
+};
+
+} // namespace Ripes
\ No newline at end of file
diff --git a/src/processors/branch/predictors/global_predictor.h b/src/processors/branch/predictors/global_predictor.h
new file mode 100644
index 000000000..10a8f0c89
--- /dev/null
+++ b/src/processors/branch/predictors/global_predictor.h
@@ -0,0 +1,142 @@
+#pragma once
+
+#include "../ripesbranchpredictor.h"
+
+namespace Ripes {
+
+template
+class GlobalPredictor : public RipesBranchPredictor {
+ static_assert(std::is_same::value ||
+ std::is_same::value,
+ "Only supports 32- and 64-bit variants");
+ static constexpr unsigned XLEN = sizeof(XLEN_T) * 8;
+
+public:
+ GlobalPredictor(VInt num_history_bits, VInt num_state_bits) {
+ this->num_history_bits = num_history_bits;
+ this->num_state_bits = num_state_bits;
+ this->lht.reset(new ARRAY_T[1]);
+ this->pht.reset(new ARRAY_T[1 << num_history_bits]());
+ resetPredictorState();
+ }
+
+ VInt num_history_bits = 0;
+ VInt num_state_bits = 0;
+
+ bool getPrediction(XLEN_T addr, bool is_branch,
+ bool is_conditional) override {
+ Q_UNUSED(addr);
+ if (is_branch && !is_conditional) {
+ return true;
+ }
+
+ else if (!is_conditional) {
+ return false;
+ }
+
+ ARRAY_T history = this->lht.get()[0];
+
+ ARRAY_T prediction_state = this->pht.get()[history];
+
+ switch (prediction_state >> (num_state_bits - 1)) {
+ case 0:
+ return false;
+ case 1:
+ return true;
+ default:
+ return false;
+ }
+ }
+
+ void updatePrediction(XLEN_T addr, bool predict_taken, bool miss,
+ bool is_branch, bool is_conditional) override {
+ Q_UNUSED(addr);
+ Q_UNUSED(is_branch);
+ if (!is_conditional) {
+ return;
+ }
+
+ bool prev_actual_taken = predict_taken ^ miss;
+
+ ARRAY_T history = this->lht.get()[0];
+
+ this->lht.get()[0] =
+ (history | (prev_actual_taken << num_history_bits)) >> 1;
+
+ ARRAY_T prediction_state = this->pht.get()[history];
+
+ if (prev_actual_taken) {
+ if (prediction_state == (1 << num_state_bits) - 1) {
+ return;
+ } else if (prediction_state >= (1 << (num_state_bits - 1)) - 1) {
+ this->pht.get()[history] = (1 << num_state_bits) - 1;
+ } else {
+ this->pht.get()[history] += 1;
+ }
+ } else {
+ if (prediction_state == 0) {
+ return;
+ } else if (prediction_state <= (1 << (num_state_bits - 1))) {
+ this->pht.get()[history] = 0;
+ } else {
+ this->pht.get()[history] -= 1;
+ }
+ }
+ }
+
+ void setReverseStackSize(VInt size) override {
+ if (this->rev_stack_max_size > size) {
+ m_rev_history_stack.resize(size);
+ m_rev_pht_stack.resize(size);
+ }
+ }
+
+ void saveState() override {
+ m_rev_history_stack.push_front(this->lht.get()[0]);
+
+ for (int i = 0; i < (1 << num_history_bits); i++) {
+ m_rev_pht_stack.push_front(this->pht.get()[i]);
+ }
+
+ if (m_rev_history_stack.size() > this->rev_stack_max_size) {
+ m_rev_history_stack.pop_back();
+ }
+
+ if (m_rev_pht_stack.size() >
+ this->rev_stack_max_size * (1 << num_history_bits)) {
+ for (int i = 0; i < 1 << num_history_bits; i++) {
+ m_rev_pht_stack.pop_back();
+ }
+ }
+ }
+
+ void restoreState() override {
+ if (m_rev_history_stack.size() == 0) {
+ return;
+ }
+
+ if (m_rev_pht_stack.size() == 0) {
+ return;
+ }
+
+ this->lht.get()[0] = m_rev_history_stack.front();
+ m_rev_history_stack.pop_front();
+
+ for (int i = 0; i < (1 << num_history_bits); i++) {
+ this->pht.get()[(1 << num_history_bits) - i - 1] =
+ m_rev_pht_stack.front();
+ m_rev_pht_stack.pop_front();
+ }
+ }
+
+ void resetPredictorState() override {
+ this->lht.get()[0] = 0;
+ std::fill_n(this->pht.get(), 1 << num_history_bits, 0);
+ }
+
+private:
+ std::deque m_rev_history_stack;
+ std::deque m_rev_pht_stack;
+};
+
+} // namespace Ripes
\ No newline at end of file
diff --git a/src/processors/branch/predictors/local_predictor.h b/src/processors/branch/predictors/local_predictor.h
new file mode 100644
index 000000000..39641f18a
--- /dev/null
+++ b/src/processors/branch/predictors/local_predictor.h
@@ -0,0 +1,164 @@
+#pragma once
+
+#include "../ripesbranchpredictor.h"
+
+namespace Ripes {
+
+template
+class LocalPredictor : public RipesBranchPredictor {
+ static_assert(std::is_same::value ||
+ std::is_same::value,
+ "Only supports 32- and 64-bit variants");
+ static constexpr unsigned XLEN = sizeof(XLEN_T) * 8;
+
+public:
+ LocalPredictor(VInt num_address_bits, VInt num_history_bits,
+ VInt num_state_bits) {
+ this->num_address_bits = num_address_bits;
+ this->num_history_bits = num_history_bits;
+ this->num_state_bits = num_state_bits;
+ this->lht.reset(new ARRAY_T[1 << num_address_bits]());
+ this->pht.reset(new ARRAY_T[1 << num_history_bits]());
+ resetPredictorState();
+ }
+
+ VInt num_address_bits = 0;
+ VInt num_history_bits = 0;
+ VInt num_state_bits = 0;
+
+ bool getPrediction(XLEN_T addr, bool is_branch,
+ bool is_conditional) override {
+ if (is_branch && !is_conditional) {
+ return true;
+ }
+
+ else if (!is_conditional) {
+ return false;
+ }
+
+ ARRAY_T check_bits =
+ ((addr >> 2) << (XLEN - num_address_bits)) >> (XLEN - num_address_bits);
+
+ if (num_address_bits == 0) {
+ check_bits = 0;
+ }
+
+ ARRAY_T history = this->lht.get()[check_bits];
+ ARRAY_T prediction_state = this->pht.get()[history];
+
+ switch (prediction_state >> (num_state_bits - 1)) {
+ case 0:
+ return false;
+ case 1:
+ return true;
+ default:
+ return false;
+ }
+ }
+
+ void updatePrediction(XLEN_T addr, bool predict_taken, bool miss,
+ bool is_branch, bool is_conditional) override {
+ Q_UNUSED(is_branch);
+ if (!is_conditional) {
+ return;
+ }
+
+ ARRAY_T check_bits =
+ ((addr >> 2) << (XLEN - num_address_bits)) >> (XLEN - num_address_bits);
+
+ if (num_address_bits == 0) {
+ check_bits = 0;
+ }
+
+ bool prev_actual_taken = predict_taken ^ miss;
+
+ ARRAY_T history = this->lht.get()[check_bits];
+
+ this->lht.get()[check_bits] =
+ (history | (prev_actual_taken << num_history_bits)) >> 1;
+
+ ARRAY_T prediction_state = this->pht.get()[history];
+
+ if (prev_actual_taken) {
+ if (prediction_state == (1 << num_state_bits) - 1) {
+ return;
+ } else if (prediction_state >= (1 << (num_state_bits - 1)) - 1) {
+ this->pht.get()[history] = (1 << num_state_bits) - 1;
+ } else {
+ this->pht.get()[history] += 1;
+ }
+ } else {
+ if (prediction_state == 0) {
+ return;
+ } else if (prediction_state <= (1 << (num_state_bits - 1))) {
+ this->pht.get()[history] = 0;
+ } else {
+ this->pht.get()[history] -= 1;
+ }
+ }
+ }
+
+ void setReverseStackSize(VInt size) override {
+ if (this->rev_stack_max_size > size) {
+ m_rev_lht_stack.resize(size);
+ m_rev_pht_stack.resize(size);
+ }
+ }
+
+ void saveState() override {
+ for (int i = 0; i < (1 << num_address_bits); i++) {
+ m_rev_lht_stack.push_front(this->lht.get()[i]);
+ }
+
+ for (int i = 0; i < (1 << num_history_bits); i++) {
+ m_rev_pht_stack.push_front(this->pht.get()[i]);
+ }
+
+ if (m_rev_lht_stack.size() >
+ this->rev_stack_max_size * (1 << num_address_bits)) {
+ for (int i = 0; i < 1 << num_address_bits; i++) {
+ m_rev_lht_stack.pop_back();
+ }
+ }
+
+ if (m_rev_pht_stack.size() >
+ this->rev_stack_max_size * (1 << num_history_bits)) {
+ for (int i = 0; i < 1 << num_history_bits; i++) {
+ m_rev_pht_stack.pop_back();
+ }
+ }
+ }
+
+ void restoreState() override {
+ if (m_rev_lht_stack.size() == 0) {
+ return;
+ }
+
+ if (m_rev_pht_stack.size() == 0) {
+ return;
+ }
+
+ for (int i = 0; i < (1 << num_address_bits); i++) {
+ this->lht.get()[(1 << num_address_bits) - i - 1] =
+ m_rev_lht_stack.front();
+ m_rev_lht_stack.pop_front();
+ }
+
+ for (int i = 0; i < (1 << num_history_bits); i++) {
+ this->pht.get()[(1 << num_history_bits) - i - 1] =
+ m_rev_pht_stack.front();
+ m_rev_pht_stack.pop_front();
+ }
+ }
+
+ void resetPredictorState() override {
+ std::fill_n(this->lht.get(), 1 << num_address_bits, 0);
+ std::fill_n(this->pht.get(), 1 << num_history_bits, 0);
+ }
+
+private:
+ std::deque m_rev_lht_stack;
+ std::deque m_rev_pht_stack;
+};
+
+} // namespace Ripes
\ No newline at end of file
diff --git a/src/processors/branch/ripesbranchpredictor.h b/src/processors/branch/ripesbranchpredictor.h
new file mode 100644
index 000000000..d4bf228f4
--- /dev/null
+++ b/src/processors/branch/ripesbranchpredictor.h
@@ -0,0 +1,101 @@
+#pragma once
+
+#include "../../ripes_types.h"
+#include
+
+namespace Ripes {
+
+/**
+ * @brief The RipesBranchPredictor class
+ * Interface for all Ripes branch predictors. This interface is intended to be
+ * ISA-agnostic and provides a consistent interface to branch predictor
+ * algorithms. This also makes it very easy to add more algorithms to Ripes.
+ *
+ * Integer values are communicated in uin64_t variables. If the implementing
+ * processor implements a narrower register width, e.g., 32 bit, then only the
+ * lower 32 bits should be considered.
+ */
+template
+class RipesBranchPredictor {
+public:
+ RipesBranchPredictor() {}
+ virtual ~RipesBranchPredictor() {}
+
+ /**
+ * @brief getPrediction
+ *
+ * @param addr Address of current instruction
+ * @param is_branch True if current instruction is branch
+ * @param is_conditional True if current instruction is conditional
+ * @return Whether or not the current instruction is predicted
+ * to be taken
+ */
+ virtual bool getPrediction(XLEN_T addr, bool is_branch,
+ bool is_conditional) = 0;
+
+ /**
+ * @brief updatePrediction
+ *
+ * @param addr Address of previous instruction
+ * @param predict_taken True if previous instruction was predicted taken
+ * @param miss True if previous prediction was wrong
+ * @param is_branch True if previous instruction is branch
+ * @param is_conditional True if previous instruction is conditional
+ */
+ virtual void updatePrediction(XLEN_T addr, bool predict_taken, bool miss,
+ bool is_branch, bool is_conditional) = 0;
+
+ virtual void setReverseStackSize(VInt size) = 0;
+
+ /**
+ * @brief saveState/restoreState
+ *
+ * Reverse feature, makes sure that the state is consistent while reversing
+ * the processor
+ */
+ virtual void saveState() = 0;
+ virtual void restoreState() = 0;
+
+ /**
+ * @brief resetPredictorState
+ *
+ * Resets all internal state of the predictor
+ */
+ virtual void resetPredictorState() = 0;
+
+ void resetPredictorCounters() {
+ num_unconditional = 0;
+ num_unconditional_miss = 0;
+ num_conditional = 0;
+ num_conditional_miss = 0;
+ }
+
+ double getConditionalAccuracy() {
+ double num = num_conditional;
+ double num_miss = num_conditional_miss;
+ return (1.0 - (double)num_miss / (double)num) * 100.0;
+ }
+
+ double getUnconditionalAccuracy() {
+ double num = num_unconditional;
+ double num_miss = num_unconditional_miss;
+ return (1.0 - (double)num_miss / (double)num) * 100.0;
+ }
+
+ double getTotalAccuracy() {
+ double num = num_conditional + num_unconditional;
+ double num_miss = num_conditional_miss + num_unconditional_miss;
+ return (1.0 - (double)num_miss / (double)num) * 100.0;
+ }
+
+ VInt num_conditional = 0;
+ VInt num_conditional_miss = 0;
+ VInt num_unconditional = 0;
+ VInt num_unconditional_miss = 0;
+ VInt rev_stack_max_size = 0;
+ std::unique_ptr lht;
+ std::unique_ptr pht;
+ bool is_zero_take = false;
+};
+
+} // namespace Ripes
diff --git a/src/processors/interface/ripesprocessor.h b/src/processors/interface/ripesprocessor.h
index c1aa3fbbc..e5dfb39fb 100644
--- a/src/processors/interface/ripesprocessor.h
+++ b/src/processors/interface/ripesprocessor.h
@@ -304,6 +304,8 @@ class RipesProcessor {
*/
virtual long long getCycleCount() const = 0;
+ virtual bool supportsBranchPrediction() const = 0;
+
/** ======================= Signals and callbacks ======================= */
/**
* @brief clocked, reversed & reset signals
diff --git a/src/processors/layouts.qrc b/src/processors/layouts.qrc
index 3c3636d7e..7917429ba 100644
--- a/src/processors/layouts.qrc
+++ b/src/processors/layouts.qrc
@@ -4,6 +4,7 @@
RISC-V/rvss/rv_ss_standard_layout.json
RISC-V/rv5s/rv5s_standard_layout.json
RISC-V/rv5s/rv5s_extended_layout.json
+ RISC-V/rv5s_br/rv5s_br_extended_layout.json
RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_standard_layout.json
RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_extended_layout.json
RISC-V/rv5s_no_hz/rv5s_no_hz_standard_layout.json
diff --git a/test/tst_cosimulate.cpp b/test/tst_cosimulate.cpp
index 694ea73c2..5a1fe9bdc 100644
--- a/test/tst_cosimulate.cpp
+++ b/test/tst_cosimulate.cpp
@@ -93,6 +93,7 @@ private slots:
*/
void testRV6SDual() { cosimulate(ProcessorID::RV32_6S_DUAL, {"M"}); }
void testRV5S() { cosimulate(ProcessorID::RV32_5S, {"M"}); }
+ void testRV5SBR() { cosimulate(ProcessorID::RV32_5S_BR, {"M"}); }
void testRV5SNoFW() { cosimulate(ProcessorID::RV32_5S_NO_FW, {"M"}); }
};
diff --git a/test/tst_riscv.cpp b/test/tst_riscv.cpp
index 977b7ec07..d7f6e01cc 100644
--- a/test/tst_riscv.cpp
+++ b/test/tst_riscv.cpp
@@ -72,6 +72,10 @@ private slots:
runTests(ProcessorID::RV64_5S, {"M", "C"},
{RISCV64_TEST_DIR, RISCV64_C_TEST_DIR});
}
+ void testRV64_5StagePipelineBR() {
+ runTests(ProcessorID::RV64_5S_BR, {"M", "C"},
+ {RISCV64_TEST_DIR, RISCV64_C_TEST_DIR});
+ }
void testRV64_5StagePipelineNOFW() {
runTests(ProcessorID::RV64_5S_NO_FW, {"M", "C"},
{RISCV64_TEST_DIR, RISCV64_C_TEST_DIR});
@@ -89,6 +93,10 @@ private slots:
runTests(ProcessorID::RV32_5S, {"M", "C"},
{RISCV32_TEST_DIR, RISCV32_C_TEST_DIR});
}
+ void testRV32_5StagePipelineBR() {
+ runTests(ProcessorID::RV32_5S_BR, {"M", "C"},
+ {RISCV32_TEST_DIR, RISCV32_C_TEST_DIR});
+ }
void testRV32_5StagePipelineNOFW() {
runTests(ProcessorID::RV32_5S_NO_FW, {"M", "C"},
{RISCV32_TEST_DIR, RISCV32_C_TEST_DIR});