{"payload":{"pageCount":2,"repositories":[{"type":"Public","name":"litex-boards","owner":"litex-hub","isFork":false,"description":"LiteX boards files","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":6,"issueCount":28,"starsCount":369,"forksCount":280,"license":"BSD 2-Clause \"Simplified\" License","participation":[15,6,6,13,13,1,11,12,0,0,2,4,5,1,7,3,5,1,2,7,1,3,9,7,5,5,18,15,9,2,8,4,1,1,6,1,2,4,15,7,11,7,4,7,0,3,1,4,9,14,8,5],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-18T09:21:51.063Z"}},{"type":"Public","name":"zephyr-on-litex-vexriscv","owner":"litex-hub","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":3,"starsCount":12,"forksCount":10,"license":"BSD 2-Clause \"Simplified\" License","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,2,1,0,3,0,0,0,0,0,2,0,0,0,1],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-17T07:57:17.812Z"}},{"type":"Public","name":"linux","owner":"litex-hub","isFork":true,"description":"Linux kernel source tree","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":2,"issueCount":0,"starsCount":5,"forksCount":53295,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-16T22:51:46.999Z"}},{"type":"Public","name":"litespi","owner":"litex-hub","isFork":false,"description":"Small footprint and configurable SPI core","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":3,"issueCount":12,"starsCount":38,"forksCount":23,"license":"BSD 2-Clause \"Simplified\" License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-16T09:49:12.560Z"}},{"type":"Public","name":"pythondata-cpu-vexiiriscv","owner":"litex-hub","isFork":false,"description":"Python module containing verilog files/generators for VexiiRiscv CPU (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-03T10:18:27.930Z"}},{"type":"Public","name":"linux-on-litex-rocket","owner":"litex-hub","isFork":false,"description":"Run 64-bit Linux on LiteX + RocketChip","allTopics":[],"primaryLanguage":{"name":"Shell","color":"#89e051"},"pullRequestCount":1,"issueCount":5,"starsCount":182,"forksCount":19,"license":"BSD 2-Clause \"Simplified\" License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-09T15:08:21.059Z"}},{"type":"Public","name":"fpga_101","owner":"litex-hub","isFork":false,"description":"FPGA 101 lessons/labs","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":1,"issueCount":9,"starsCount":354,"forksCount":58,"license":"BSD 2-Clause \"Simplified\" License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-14T01:35:32.820Z"}},{"type":"Public","name":"pythondata-cpu-naxriscv","owner":"litex-hub","isFork":false,"description":"Python module containing verilog files/generators for NaxRiscv CPU (for use with LiteX). ","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":3,"license":"MIT License","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-10T09:16:50.396Z"}},{"type":"Public","name":"linux-on-litex-vexriscv","owner":"litex-hub","isFork":false,"description":"Linux on LiteX-VexRiscv","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":52,"starsCount":567,"forksCount":175,"license":"BSD 2-Clause \"Simplified\" License","participation":[0,0,1,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,1,0,0,0,2,0,0,15,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-09T17:44:36.270Z"}},{"type":"Public","name":"pythondata-cpu-vexriscv_smp","owner":"litex-hub","isFork":false,"description":"Python module containing verilog files for VexRiscv SMP CPU (for use with LiteX). ","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":1,"issueCount":4,"starsCount":3,"forksCount":11,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:14:07.830Z"}},{"type":"Public","name":"pythondata-cpu-vexriscv","owner":"litex-hub","isFork":true,"description":"Python module containing verilog files for vexriscv cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":3,"issueCount":0,"starsCount":7,"forksCount":39,"license":"MIT License","participation":[0,0,0,0,0,0,0,3,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:14:04.274Z"}},{"type":"Public","name":"pythondata-cpu-serv","owner":"litex-hub","isFork":false,"description":"Python module containing verilog files for serv cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":6,"forksCount":2,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:14:02.420Z"}},{"type":"Public","name":"pythondata-cpu-rocket","owner":"litex-hub","isFork":false,"description":"Python module containing verilog files for rocket cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":13,"forksCount":8,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:59.032Z"}},{"type":"Public","name":"pythondata-cpu-picorv32","owner":"litex-hub","isFork":false,"description":"Python module containing verilog files for picorv32 cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":0,"license":"Other","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:57.491Z"}},{"type":"Public","name":"pythondata-cpu-minerva","owner":"litex-hub","isFork":false,"description":"Python module containing sources files for minerva cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"BSD 2-Clause \"Simplified\" License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:52.078Z"}},{"type":"Public","name":"pythondata-cpu-ibex","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for ibex cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":0,"starsCount":2,"forksCount":3,"license":"Apache License 2.0","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:49.588Z"}},{"type":"Public","name":"pythondata-cpu-cva6","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for cva6 cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":0,"starsCount":2,"forksCount":4,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:47.369Z"}},{"type":"Public","name":"pythondata-cpu-cva5","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for cva5 cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":0,"license":"Apache License 2.0","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:44.442Z"}},{"type":"Public","name":"pythondata-cpu-cv32e41p","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for cv32e41p cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":1,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:42.520Z"}},{"type":"Public","name":"pythondata-cpu-cv32e40p","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for cv32e40p cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":6,"license":"Other","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:40.546Z"}},{"type":"Public","name":"pythondata-cpu-blackparrot","owner":"litex-hub","isFork":false,"description":"Python module containing system_verilog files for blackparrot cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":5,"forksCount":3,"license":"BSD 3-Clause \"New\" or \"Revised\" License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:37.597Z"}},{"type":"Public","name":"pythondata-cpu-microwatt","owner":"litex-hub","isFork":false,"description":"Python module containing vhdl files for microwatt cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"VHDL","color":"#adb2cb"},"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":0,"license":"Creative Commons Attribution Share Alike 4.0 International","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:35.585Z"}},{"type":"Public","name":"pythondata-cpu-marocchino","owner":"litex-hub","isFork":false,"description":"Python module containing verilog files for marocchino cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":0,"license":"Mozilla Public License 2.0","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:33.716Z"}},{"type":"Public","name":"pythondata-cpu-mor1kx","owner":"litex-hub","isFork":false,"description":"Python module containing verilog files for mor1kx cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":1,"issueCount":0,"starsCount":1,"forksCount":1,"license":"Mozilla Public License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:30.945Z"}},{"type":"Public","name":"pythondata-cpu-lm32","owner":"litex-hub","isFork":false,"description":"Python module containing verilog files for lm32 cpu (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":1,"license":"Eclipse Public License 1.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:28.788Z"}},{"type":"Public","name":"pythondata-misc-usb_ohci","owner":"litex-hub","isFork":false,"description":"Python module containing verilog files for the Spinal-HDL USB OHCI core (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:26.910Z"}},{"type":"Public","name":"pythondata-misc-tapcfg","owner":"litex-hub","isFork":false,"description":"Python module containing data files for tapcfg misc (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":0,"license":"GNU Lesser General Public License v2.1","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:13:24.962Z"}},{"type":"Public","name":"pythondata-software-compiler_rt","owner":"litex-hub","isFork":false,"description":"Python module containing data files for compiler_rt software (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":2,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:12:44.900Z"}},{"type":"Public","name":"pythondata-software-picolibc","owner":"litex-hub","isFork":false,"description":"Python module containing data files for picolibc software (for use with LiteX).","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":2,"license":"BSD 3-Clause \"New\" or \"Revised\" License","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:12:42.948Z"}},{"type":"Public","name":"pythondata-auto","owner":"litex-hub","isFork":false,"description":"Scripts which automate the creation of the `litex.data` Python modules from various git repositories.","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":9,"starsCount":4,"forksCount":10,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-14T10:11:10.048Z"}}],"repositoryCount":54,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"litex-hub repositories"}