From eb8d9756378b010f71b624684f9765dd8e649f9f Mon Sep 17 00:00:00 2001
From: aottaviano <aottaviano@iis.ee.ethz.ch>
Date: Sat, 20 Jul 2024 10:27:29 +0200
Subject: [PATCH] hw: Add VFCVT(U)_D_S instruction

---
 hw/snitch/src/riscv_instr.sv          |  2 ++
 hw/snitch/src/snitch.sv               | 13 +++++++++++++
 hw/snitch_cluster/src/snitch_fp_ss.sv | 10 ++++++++++
 3 files changed, 25 insertions(+)

diff --git a/hw/snitch/src/riscv_instr.sv b/hw/snitch/src/riscv_instr.sv
index b415628af..5bd5165fb 100644
--- a/hw/snitch/src/riscv_instr.sv
+++ b/hw/snitch/src/riscv_instr.sv
@@ -704,6 +704,8 @@ package riscv_instr;
   localparam logic [31:0] VFCVTU_S_B         = 32'b100110000111?????100?????0110011;
   localparam logic [31:0] VFCVT_B_S          = 32'b100110000100?????011?????0110011;
   localparam logic [31:0] VFCVTU_B_S         = 32'b100110000100?????111?????0110011;
+  localparam logic [31:0] VFCVT_D_S          = 32'b100110000100?????001?????0110011;
+  localparam logic [31:0] VFCVTU_D_S         = 32'b100110000100?????101?????0110011;
   localparam logic [31:0] VFCVT_H_B          = 32'b100110000111?????010?????0110011;
   localparam logic [31:0] VFCVTU_H_B         = 32'b100110000111?????110?????0110011;
   localparam logic [31:0] VFCVT_B_H          = 32'b100110000110?????011?????0110011;
diff --git a/hw/snitch/src/snitch.sv b/hw/snitch/src/snitch.sv
index fb46914e8..060b7ff94 100644
--- a/hw/snitch/src/snitch.sv
+++ b/hw/snitch/src/snitch.sv
@@ -1354,6 +1354,19 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
           illegal_inst = 1'b1;
         end
       end
+      VFCVT_D_S,
+      VFCVTU_D_S: begin
+        if (FP_EN && XFVEC && RVF && FLEN >= 32) begin
+          if (RVF && RVD) begin
+            write_rd = 1'b0;
+            acc_qvalid_o = valid_instr;
+          end else begin
+            illegal_inst = 1'b1;
+          end
+        end else begin
+          illegal_inst = 1'b1;
+        end
+      end
       VFCVT_S_H,
       VFCVTU_S_H: begin
         if (FP_EN && XFVEC && RVF && FLEN >= 32) begin
diff --git a/hw/snitch_cluster/src/snitch_fp_ss.sv b/hw/snitch_cluster/src/snitch_fp_ss.sv
index 1df5b0793..ee1291052 100644
--- a/hw/snitch_cluster/src/snitch_fp_ss.sv
+++ b/hw/snitch_cluster/src/snitch_fp_ss.sv
@@ -528,6 +528,16 @@ module snitch_fp_ss import snitch_pkg::*; #(
         vectorial_op = 1'b1;
         set_dyn_rm   = 1'b1;
       end
+      riscv_instr::VFCVT_D_S,
+      riscv_instr::VFCVTU_D_S: begin
+        fpu_op = fpnew_pkg::F2F;
+        op_select[0] = RegA;
+        src_fmt      = fpnew_pkg::FP32;
+        dst_fmt      = fpnew_pkg::FP64;
+        vectorial_op = 1'b1;
+        set_dyn_rm   = 1'b1;
+        if (acc_req_q.data_op inside {riscv_instr::VFCVTU_D_S}) op_mode = 1'b1;
+      end
       // Double Precision
       riscv_instr::FADD_D: begin
         fpu_op = fpnew_pkg::ADD;