A lightweight JIT compiler based on MIR (Medium Internal Representation) and C11 JIT compiler and interpreter based on MIR
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Updated
Jun 20, 2024 - C
A lightweight JIT compiler based on MIR (Medium Internal Representation) and C11 JIT compiler and interpreter based on MIR
The RISC-V Virtual Machine
A Github Action that executes jobs/commands on non-x86 cpu architectures (ARMv6, ARMv7, aarch64, s390x, ppc64le, riscv64) via QEMU
The Adventures of OS
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
The juice virtual machine was born in 2020, with the goal of realizing the smallest virtual machine of RISC-V that can run the latest kernel mainline. At the beginning of the design, it runs on a platform with only 100 KB of RAM, which does not exceed the number of C99. Three-party dependence.
World Of Warcraft 3.3.5a server
F# RISC-V Instruction Set formal specification
UART based embedded shell for embedded systems. Intended to be used for learning, experimenting and diagnostics.
Standalone C compiler/assembler/linker/libc for x86-64/aarch64/riscv64/wasm
A curated list of awesome MangoPi MQ-Pro images, tools and resources
Simple risc-v emulator, able to run linux, written in C.
😎 A curated list of awesome RISC-V implementations
OpenCar riscv emulator written in java openCar 主要完成一款仿真Riscv指令集的软件,目标是提供基础的Rv指令模拟环境,同时支持各芯片方基于openCar扩展指令以实现趋近于芯片功能的仿真环境,为异构的软件生态提供方便的调试观察功能。
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