Skip to content

Fahad-Habib/RISC-V-Pipelined-Processor-with-CSR

BranchesTags

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

2 Commits
ALU.sv
ALU.sv
 
 
Add4 .sv
Add4 .sv
 
 
BranchCondition.sv
BranchCondition.sv
 
 
CSR_RegisterFile.sv
CSR_RegisterFile.sv
 
 
CSR_buffer.sv
CSR_buffer.sv
 
 
Controller.sv
Controller.sv
 
 
DataMemory.sv
DataMemory.sv
 
 
ForwardingUnit.sv
ForwardingUnit.sv
 
 
ImmediateGenerator.sv
ImmediateGenerator.sv
 
 
InstructionMemory.sv
InstructionMemory.sv
 
 
Mux2.sv
Mux2.sv
 
 
PC.sv
PC.sv
 
 
PipelineControl.sv
PipelineControl.sv
 
 
PipelineRegister.sv
PipelineRegister.sv
 
 
Pipeline_Branch.sv
Pipeline_Branch.sv
 
 
Pipeline_IR.sv
Pipeline_IR.sv
 
 
Processor.sv
Processor.sv
 
 
README.md
README.md
 
 
RegisterFile.sv
RegisterFile.sv
 
 
WriteBack.sv
WriteBack.sv
 
 

Repository files navigation

RISC-V-Pipelined-Processor-with-CSR

A 3-stage Pipelined Processor written from scratch in SystemVerilog for executing the machine code of RISC-V ISA with interrupt CSR (Control and Status Register). RISC-V is an open standard instruction set architecture based on established reduced instruction set computer principles.

Instruction Types

The instruction types implemented in this project are:

  • R-type
  • I-type
  • S-type
  • B-type
  • J-type
  • U-type
  • CSRRW
  • MRET

Support this project by leaving a ⭐

About

3-stage RISC-V Pipelined Processor with interrupt CSR support

Topics

systemverilog risc-v digital-system-design risc-v-assembly risc-v-architecture

Resources

Readme
Activity

Stars

2 stars

Watchers

1 watching

Forks

0 forks
Report repository

Releases

No releases published

Packages

No packages published

Languages