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convolutional-code-logic-design

The Project

VHDL (acronym for VHSIC Hardware Description Language, where "VHSIC" stands for Very High Speed Integrated Circuits) is the fundamental tool for digital circuits design.

The aim of this project was to design, implement and synthesize a hardware module that serves as a convolutional code and that satisfies certain requirements.

The component was designed and tested using Xilinx Vivado. FPGA target is Xilinx Artix-7 xc7a200tfbg484-1.

For further informations about module implementation and testing results please consult report.pdf a link

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