Skip to content
View PaoloC96's full-sized avatar
Block or Report

Block or report PaoloC96

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. Reti-Logiche-Capra-Chiudinelli Reti-Logiche-Capra-Chiudinelli Public archive

    Vhdl project for Reti Logiche Prova Finale

    VHDL 1

  2. ing-sw-2019-Buratti-Capra-Chiudinelli ing-sw-2019-Buratti-Capra-Chiudinelli Public archive

    Progetto per prova finale del corso di ingegneria del software

    Java