Runtime data input from Python to VHDL

[suryabvsp]

I am trying to understand if there is a way to write data to VHDL signals from Python in runtime. This could also be possible if message passing can be done between Python and VHDL, about which I could not find references in the user guide. There could also be a simpler way that I might be missing.

In other words, I am not looking for creating multiple test cases, but to manipulate inputs to a VHDL module in runtime within a single test case.

I would really appreciate some clarification on this topic.

Not sure if #603 talks about the exact same thing.

[LarsAsplund]

There has been some work in this area, see https://vunit.github.io/cosim/. There is a also development branch targeting embedded Python in VHDL, see example. This is a first step towards a tighter run-time integration with VHDL. The second step is to do message passing between Python and VHDL.