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Issues: VUnit/vunit
[Breaking Change] Deprecation of 'compile_builtins' and remov...
#777
opened Nov 13, 2021 by
umarcor
Open
2
News fragments of the contributions/modifications done in the...
#997
by umarcor
was closed Jul 19, 2024
Closed
1
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[FEATURE] Print/save commands outputs/logs from (ModelSim/QuestaSim/Questa Base)
#1057
opened Sep 12, 2024 by
nselvara
Regression: exploded stack in log function when running with Acitve-HDL
#1045
opened Jul 24, 2024 by
jobtijhuis
Is there a way to specify minimum cycles between stalls for AXI stream VC?
#1013
opened May 1, 2024 by
cjmeyer
Question about "blocking" specifically around the bus_master VCI
#1012
opened May 1, 2024 by
nathanaelhuffman
How to specify test case(s) to run after creating a VUnit instance?
#1010
opened Apr 23, 2024 by
cjmeyer
VUnit testcases fail if the testcase name contains a colon (SystemVerilog)
#1009
opened Apr 17, 2024 by
PossenigM
VUnit testcases fail if the last character in a testcase name is a whitespace (VHDL)
Bug
#1008
opened Apr 17, 2024 by
PossenigM
Support for CI (reruns) with waveform output
CI
Enhancement
Question
Tool: Surfer
#1003
opened Mar 13, 2024 by
oscargus
Feature Request: real_array_t similar to integer_array_t
Builtins
Enhancement
#999
opened Mar 11, 2024 by
abaebae
Feature Request: Support for adding .psl files to allow for Assertion Based Verification
#976
opened Nov 9, 2023 by
vhdlp
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