[CODEGEN] ARM Popcount lowering rule and codegen updates #1235
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…ing and accessing vectors
tqchen
changed the title
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There is an unintended change that reverts the submodule to an older version. Please update the submodule (HalideIR) to the latest version. You can do it by git pull under the HalideIR folder |
src/codegen/llvm/codegen_llvm.cc
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| @@ -366,7 +366,7 @@ llvm::Value* CodeGenLLVM::CreateBroadcast(llvm::Value* value, int lanes) { | |||
| llvm::Value* CodeGenLLVM::CreateVecSlice(llvm::Value* vec, int begin, int extent) { | |||
| int num_elems = static_cast<int>(vec->getType()->getVectorNumElements()); | |||
| if (extent == num_elems && begin == 0) return vec; | |||
| CHECK_LT(begin + extent, num_elems); | |||
| CHECK_LT(begin + extent, num_elems+1); | |||
| return CodeGenCPU::CreateIntrinsic(op); | ||
| } | ||
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| Expr CodeGenARM::ARMPopcount(const Call *call) { |
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We will need a regression test for this rule. please add a test case to arm popcount, to a new file tests/python/unittest/test_codegen_arm.py .
Since we don't have ARM device to verify, what we can do is to dump out the asm file(Maybe we can patch GetSource in llvm module to support get_source("asm") ) and verify the neons sequence is as expected.
src/codegen/llvm/codegen_arm.cc
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| ::llvm::Intrinsic::ID vpaddu_id = ::llvm::Intrinsic::arm_neon_vpaddlu; | ||
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| Type uint8_type = Type(e.type().code(), 8, e.type().bits() * e.type().lanes() / 8); |
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move the typedef after the fallback guard, add comment that the division is always dividable.
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Add a comment about what this specific pattern of neon sequence is
tqchen
added
status: accepted
and removed
status: need update
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Thanks, this is merged! |
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Nice! |
TVM compiler changes for low precision operators
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