*New command:Verilog format can be changed and ABC can read it

[yuzy111]

abc can not read
/---------------------------------------------------------------------------------------/
assign { 029[30:3], 029[0] } = { 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], 029[31], cnt[0] };
/---------------------------------------------------------------------------------------/
I can convert it into
/---------------------------------------------------------------------------------------/
assign 029[30] = 029[31];
assign 029[29] = 029[31];
assign 029[28] = 029[31];
assign 029[27] = 029[31];
assign 029[26] = 029[31];
assign 029[25] = 029[31];
assign 029[24] = 029[31];
assign 029[23] = 029[31];
assign 029[22] = 029[31];
assign 029[21] = 029[31];
assign 029[20] = 029[31];
assign 029[19] = 029[31];
assign 029[18] = 029[31];
assign 029[17] = 029[31];
assign 029[16] = 029[31];
assign 029[15] = 029[31];
assign 029[14] = 029[31];
assign 029[13] = 029[31];
assign 029[12] = 029[31];
assign 029[11] = 029[31];
assign 029[10] = 029[31];
assign 029[9] = 029[31];
assign 029[8] = 029[31];
assign 029[7] = 029[31];
assign 029[6] = 029[31];
assign 029[5] = 029[31];
assign 029[4] = 029[31];
assign 029[3] = 029[31];
assign 029[0] = cnt[0];
/---------------------------------------------------------------------------------------/

usage: read_verilog
read Verilog
inputfile : the name of a file to read
outputfile : the name of a file to write

[yuzy111]

ABC can read the second format