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ARM64-SVE: Fix conditional select for Zeroing predicates #102904 #105737

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Aug 13, 2024
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ARM64-SVE: Fix conditional select for Zeroing predicates #102904 #105737

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e4473d5
ARM64-SVE: Fix conditional select for Zeroing predicates
a74nh Jul 30, 2024
b338154
Allow if conditional select op3 is all zeros
a74nh Jul 31, 2024
21156d4
Merge main
a74nh Aug 5, 2024
158ff30
Remove tabs
a74nh Aug 5, 2024
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Merge main
a74nh Aug 6, 2024
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a74nh Aug 6, 2024
e8967ec
Merge main
a74nh Aug 12, 2024
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Merge main
a74nh Aug 13, 2024
737cb38
Merge branch 'main' into selectz_github
a74nh Aug 13, 2024
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18 changes: 13 additions & 5 deletions src/coreclr/jit/hwintrinsic.h
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Original file line number Diff line number Diff line change
Expand Up @@ -236,16 +236,18 @@ enum HWIntrinsicFlag : unsigned int
// then the intrinsic should be switched to a scalar only version.
HW_Flag_HasScalarInputVariant = 0x2000000,

// The intrinsic uses a mask in arg1 to select elements present in the result, and must use a low vector register.
HW_Flag_LowVectorOperation = 0x4000000,

// The intrinsic uses a mask in arg1 to select elements present in the result, which zeros inactive elements
// (instead of merging).
HW_Flag_ZeroingMaskedOperation = 0x8000000,

#endif // TARGET_XARCH

// The intrinsic is a FusedMultiplyAdd intrinsic
HW_Flag_FmaIntrinsic = 0x40000000,

#if defined(TARGET_ARM64)
// The intrinsic uses a mask in arg1 to select elements present in the result, and must use a low vector register.
HW_Flag_LowVectorOperation = 0x4000000,
#endif

HW_Flag_CanBenefitFromConstantProp = 0x80000000,
};

Expand Down Expand Up @@ -955,6 +957,12 @@ struct HWIntrinsicInfo
return (flags & HW_Flag_HasScalarInputVariant) != 0;
}

static bool IsZeroingMaskedOperation(NamedIntrinsic id)
{
const HWIntrinsicFlag flags = lookupFlags(id);
return (flags & HW_Flag_ZeroingMaskedOperation) != 0;
}

static NamedIntrinsic GetScalarInputVariant(NamedIntrinsic id)
{
assert(HasScalarInputVariant(id));
Expand Down
158 changes: 79 additions & 79 deletions src/coreclr/jit/hwintrinsiclistarm64sve.h
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6 changes: 5 additions & 1 deletion src/coreclr/jit/lowerarmarch.cpp
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Expand Up @@ -4028,9 +4028,13 @@ GenTree* Lowering::LowerHWIntrinsicCndSel(GenTreeHWIntrinsic* cndSelNode)
// `trueValue`
GenTreeHWIntrinsic* nestedCndSel = op2->AsHWIntrinsic();
GenTree* nestedOp1 = nestedCndSel->Op(1);
GenTree* nestedOp2 = nestedCndSel->Op(2);
assert(varTypeIsMask(nestedOp1));
assert(nestedOp2->OperIsHWIntrinsic());

if (nestedOp1->IsMaskAllBitsSet())
NamedIntrinsic nestedOp2Id = nestedOp2->AsHWIntrinsic()->GetHWIntrinsicId();

if (nestedOp1->IsMaskAllBitsSet() && !HWIntrinsicInfo::IsZeroingMaskedOperation(nestedOp2Id))
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{
GenTree* nestedOp2 = nestedCndSel->Op(2);
GenTree* nestedOp3 = nestedCndSel->Op(3);
Expand Down
12 changes: 1 addition & 11 deletions src/tests/JIT/HardwareIntrinsics/Arm/Shared/SveGatherVectorByteOffsets.template
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Expand Up @@ -56,17 +56,7 @@ namespace JIT.HardwareIntrinsics.Arm
test.RunStructFldScenario();

// Validates using inside ConditionalSelect with value falseValue
// Currently, using this operation in ConditionalSelect() gives incorrect result
// when falseReg == targetReg because this instruction uses Pg/Z to update the targetReg
// instead of Pg/M to merge it. As such, the value of falseReg is lost. Ideally, such
// instructions should be marked similar to RMW (a different flag name) to make sure that
// we do not assign falseReg/targetReg same. Then, we would do something like this:
//
// ldnf1sh target, pg/z, [x0]
// sel mask, target, target, falseReg
//
// This needs more careful thinking, so disabling it for now.
// test.ConditionalSelect_FalseOp();
test.ConditionalSelect_FalseOp();

// Validates using inside ConditionalSelect with zero falseValue
test.ConditionalSelect_ZeroOp();
Expand Down
12 changes: 1 addition & 11 deletions src/tests/JIT/HardwareIntrinsics/Arm/Shared/SveGatherVectorIndices.template
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Expand Up @@ -56,17 +56,7 @@ namespace JIT.HardwareIntrinsics.Arm
test.RunStructFldScenario();

// Validates using inside ConditionalSelect with value falseValue
// Currently, using this operation in ConditionalSelect() gives incorrect result
// when falseReg == targetReg because this instruction uses Pg/Z to update the targetReg
// instead of Pg/M to merge it. As such, the value of falseReg is lost. Ideally, such
// instructions should be marked similar to RMW (a different flag name) to make sure that
// we do not assign falseReg/targetReg same. Then, we would do something like this:
//
// ldnf1sh target, pg/z, [x0]
// sel mask, target, target, falseReg
//
// This needs more careful thinking, so disabling it for now.
// test.ConditionalSelect_FalseOp();
test.ConditionalSelect_FalseOp();

// Validates using inside ConditionalSelect with zero falseValue
test.ConditionalSelect_ZeroOp();
Expand Down
12 changes: 1 addition & 11 deletions src/tests/JIT/HardwareIntrinsics/Arm/Shared/SveGatherVectorVectorBases.template
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Expand Up @@ -56,17 +56,7 @@ namespace JIT.HardwareIntrinsics.Arm
test.RunStructFldScenario();

// Validates using inside ConditionalSelect with value falseValue
// Currently, using this operation in ConditionalSelect() gives incorrect result
// when falseReg == targetReg because this instruction uses Pg/Z to update the targetReg
// instead of Pg/M to merge it. As such, the value of falseReg is lost. Ideally, such
// instructions should be marked similar to RMW (a different flag name) to make sure that
// we do not assign falseReg/targetReg same. Then, we would do something like this:
//
// ldnf1sh target, pg/z, [x0]
// sel mask, target, target, falseReg
//
// This needs more careful thinking, so disabling it for now.
// test.ConditionalSelect_FalseOp();
test.ConditionalSelect_FalseOp();

// Validates using inside ConditionalSelect with zero falseValue
test.ConditionalSelect_ZeroOp();
Expand Down
12 changes: 1 addition & 11 deletions src/tests/JIT/HardwareIntrinsics/Arm/Shared/SveLoadNonFaultingUnOpTest.template
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Expand Up @@ -47,17 +47,7 @@ namespace JIT.HardwareIntrinsics.Arm
test.RunStructFldScenario();

// Validates using inside ConditionalSelect with value falseValue
// Currently, using this operation in ConditionalSelect() gives incorrect result
// when falseReg == targetReg because this instruction uses Pg/Z to update the targetReg
// instead of Pg/M to merge it. As such, the value of falseReg is lost. Ideally, such
// instructions should be marked similar to RMW (a different flag name) to make sure that
// we do not assign falseReg/targetReg same. Then, we would do something like this:
//
// ldnf1sh target, pg/z, [x0]
// sel mask, target, target, falseReg
//
// This needs more careful thinking, so disabling it for now.
// test.ConditionalSelect_FalseOp();
test.ConditionalSelect_FalseOp();

// Validates using inside ConditionalSelect with zero falseValue
test.ConditionalSelect_ZeroOp();
Expand Down
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