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[RISC-V] Fix GenerateResolveStub #106562

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merged 1 commit into from
Aug 22, 2024
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t-mustafin
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Fix to allow use of fast cached way.

Part of #84834 cc @dotnet/samsung

Draft to check test results.

Fix to allow use of fast cached way.
@dotnet-policy-service dotnet-policy-service bot added the community-contribution Indicates that the PR has been added by a community member label Aug 16, 2024
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risc-vv commented Aug 16, 2024

4e62495 is being scheduled for building and testing

GIT: 4e62495598ece7520bb67b8e77af93a1222840fa
REPO: t-mustafin/runtime
BRANCH: fix_GenerateResolveStub

Release-build FAILED

buildinfo.json
${{details}}

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t-mustafin commented Aug 16, 2024

ResolveStub uses cache of resolved methods, bug leads to cache miss every time. So this PR does not fix any test, otherwise may show some new fail.

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This PR does not makes new fails on checked coreclr tests on default, jitstress0x2 and jitstressregs0x2 launches. gcstress0xc has ~207 fails for both orig/patched, 25 of them differs. I suppose there is some issue which makes tests fail intermittently on gcstress mode not connected with this PR.

@t-mustafin t-mustafin marked this pull request as ready for review August 21, 2024 17:19
@t-mustafin t-mustafin marked this pull request as draft August 21, 2024 18:52
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Need to check code one more time tomorrow.

@t-mustafin t-mustafin marked this pull request as ready for review August 22, 2024 10:57
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Disasm collected with gdb looks ok. Disasm orig:

   0x0000003f274f2ce8:  ld      t3,0(a0)
   0x0000003f274f2cec:  srli    t0,t3,0xc
   0x0000003f274f2cf0:  add     t1,t3,t0
   0x0000003f274f2cf4:  auipc   t0,0x0
   0x0000003f274f2cf8:  addi    t0,t0,-12 # 0x3f274f2ce8
   0x0000003f274f2cfc:  lw      t6,132(t0)
   0x0000003f274f2d00:  xor     t1,t1,t6
   0x0000003f274f2d04:  lui     t6,0x7ff8
   0x0000003f274f2d08:  srliw   t6,t6,0xc
   0x0000003f274f2d0c:  and     t1,t1,t6
   0x0000003f274f2d10:  ld      t6,144(t0)
   0x0000003f274f2d14:  add     t1,t6,t1
   0x0000003f274f2d18:  ld      t1,0(t1)
   0x0000003f274f2d1c:  ld      t6,0(t1)
   0x0000003f274f2d20:  ld      t2,152(t0)
   0x0000003f274f2d24:  bne     t6,t3,0x3f274f2d38
   0x0000003f274f2d28:  ld      t6,0(t1)                       <--- Fix 1
   0x0000003f274f2d2c:  bne     t6,t2,0x3f274f2d38
   0x0000003f274f2d30:  .4byte  0x37e03                        <--- Fix 2
   0x0000003f274f2d34:  jr      t3
   0x0000003f274f2d38:  auipc   t0,0x0
   0x0000003f274f2d3c:  ld      t6,80(t0) # 0x3f274f2d88
   0x0000003f274f2d40:  ld      t2,72(t0)
   0x0000003f274f2d44:  jr      t6 # 0x7ff8000
   0x0000003f274f2d48:  auipc   t0,0x0
   0x0000003f274f2d4c:  ld      t1,40(t0) # 0x3f274f2d70
   0x0000003f274f2d50:  lw      t6,0(t1)
   0x0000003f274f2d54:  addi    t6,t6,-1
   0x0000003f274f2d58:  sw      t6,0(t1)
   0x0000003f274f2d5c:  slti    t6,t6,0
   0x0000003f274f2d60:  xori    t6,t6,1
   0x0000003f274f2d64:  or      t5,t5,t6
   0x0000003f274f2d68:  j       0x3f274f2ce8

Disasm patched:

   0x0000003f781d64c8:  ld      t3,0(a0)
   0x0000003f781d64cc:  srli    t0,t3,0xc
   0x0000003f781d64d0:  add     t1,t3,t0
   0x0000003f781d64d4:  auipc   t0,0x0
   0x0000003f781d64d8:  addi    t0,t0,-12 # 0x3f781d64c8
   0x0000003f781d64dc:  lw      t6,132(t0)
   0x0000003f781d64e0:  xor     t1,t1,t6
   0x0000003f781d64e4:  lui     t6,0x7ff8
   0x0000003f781d64e8:  srliw   t6,t6,0xc
   0x0000003f781d64ec:  and     t1,t1,t6
   0x0000003f781d64f0:  ld      t6,144(t0)
   0x0000003f781d64f4:  add     t1,t6,t1
   0x0000003f781d64f8:  ld      t1,0(t1)
   0x0000003f781d64fc:  ld      t6,0(t1)
   0x0000003f781d6500:  ld      t2,152(t0)
   0x0000003f781d6504:  bne     t6,t3,0x3f781d6518
   0x0000003f781d6508:  ld      t6,8(t1)                               <--- Fix 1
   0x0000003f781d650c:  bne     t6,t2,0x3f781d6518
   0x0000003f781d6510:  ld      t3,16(t1)                              <--- Fix 2
   0x0000003f781d6514:  jr      t3
   0x0000003f781d6518:  auipc   t0,0x0
   0x0000003f781d651c:  ld      t6,80(t0) # 0x3f781d6568
   0x0000003f781d6520:  ld      t2,72(t0)
   0x0000003f781d6524:  jr      t6 # 0x7ff8000
   0x0000003f781d6528:  auipc   t0,0x0
   0x0000003f781d652c:  ld      t1,40(t0) # 0x3f781d6550
   0x0000003f781d6530:  lw      t6,0(t1)
   0x0000003f781d6534:  addi    t6,t6,-1
   0x0000003f781d6538:  sw      t6,0(t1)
   0x0000003f781d653c:  slti    t6,t6,0
   0x0000003f781d6540:  xori    t6,t6,1
   0x0000003f781d6544:  or      t5,t5,t6
   0x0000003f781d6548:  j       0x3f781d64c8

@am11 am11 requested a review from jkotas August 22, 2024 14:14
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jkotas commented Aug 22, 2024

/ba-g This is a helix work item crash with status: DeadLetter. These tests are not relevant to this change.

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Thanks

@jkotas jkotas merged commit 581ea9d into dotnet:main Aug 22, 2024
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