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Use zero register in csel when possible #78330

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Nov 16, 2022
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7 changes: 5 additions & 2 deletions src/coreclr/jit/codegenarm64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4746,9 +4746,12 @@ void CodeGen::genCodeForSelect(GenTreeConditional* tree)
prevCond = GenCondition::NE;
}

assert(!op1->isContained() || op1->IsIntegralConst(0));
assert(!op2->isContained() || op2->IsIntegralConst(0));

regNumber targetReg = tree->GetRegNum();
regNumber srcReg1 = genConsumeReg(op1);
regNumber srcReg2 = genConsumeReg(op2);
regNumber srcReg1 = op1->IsIntegralConst(0) ? REG_ZR : genConsumeReg(op1);
regNumber srcReg2 = op2->IsIntegralConst(0) ? REG_ZR : genConsumeReg(op2);
const GenConditionDesc& prevDesc = GenConditionDesc::Get(prevCond);

emit->emitIns_R_R_R_COND(INS_csel, attr, targetReg, srcReg1, srcReg2, JumpKindToInsCond(prevDesc.jumpKind1));
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8 changes: 4 additions & 4 deletions src/coreclr/jit/emitarm64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -525,8 +525,8 @@ void emitter::emitInsSanityCheck(instrDesc* id)
case IF_DR_3D: // DR_3D X..........mmmmm cccc..nnnnnmmmmm Rd Rn Rm cond
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
assert(isGeneralRegisterOrZR(id->idReg2()));
assert(isGeneralRegisterOrZR(id->idReg3()));
assert(isValidImmCond(emitGetInsSC(id)));
break;

Expand Down Expand Up @@ -7345,8 +7345,8 @@ void emitter::emitIns_R_R_R_COND(
case INS_csinv:
case INS_csneg:
assert(isGeneralRegister(reg1));
assert(isGeneralRegister(reg2));
assert(isGeneralRegister(reg3));
assert(isGeneralRegisterOrZR(reg2));
assert(isGeneralRegisterOrZR(reg3));
cfi.cond = cond;
fmt = IF_DR_3D;
break;
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7 changes: 7 additions & 0 deletions src/coreclr/jit/lowerarmarch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2463,6 +2463,13 @@ void Lowering::ContainCheckSelect(GenTreeConditional* node)
ContainCheckCompare(startOfChain->AsOp());
}
}

if(node->gtOp1->IsIntegralConst(0)) {
MakeSrcContained(node, node->gtOp1);
}
if(node->gtOp2->IsIntegralConst(0)) {
MakeSrcContained(node, node->gtOp2);
}
}

#endif // TARGET_ARM64
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