Adding more rule tables to the documentation.

docs/rules.rst

@@ -7,6 +7,20 @@ SkyWater SKY130 Process Design Rules
     :maxdepth: 2
 
     rules/background
+    rules/masks
+
     rules/assumptions
+
+    rules/layers
+
+    rules/summary
+
     rules/periphery
+    rules/wlcsp
+    rules/hv
+
+    rules/antenna
+
+    rules/rcx
+
     rules/errors

docs/rules/antenna.rst

@@ -0,0 +1,85 @@
+Antenna Rules
+=============
+
+Antenna rules specify the maximum allowed ratio of interconnect area exposed to plasma etch to active gate poly area that is electrically connected to it when the interconnect is etched. Interconnect areas exposed to plasma etch are:
+
+* bottom areas of Licon, Mcon, Via, Via2
+
+* perimeter areas of connection layers Poly, Li, Met1, Met2, Met3
+
+Two types of checks are introduced in the following tables:
+
+* vertical for perimeter area, and
+
+* horizontal for contact area
+
+The numbers checked for are in the MAX_EGAR column.
+
+Definitions
+-----------
+
+.. csv-table:: Antenna Rules Definitions
+   :file: antenna/definitions.csv
+   :header-rows: 1
+   :stub-columns: 1
+
+Antenna rule numbers depend on the connection to the following devices:
+
+pAntennaShort = (tap AndNot poly) AndNot nwell
+  It is a p+ tap contact used to shortcut to substrate ground buses.
+
+AntennaDiode = (diff OR tap) AndNot (poly OR pAntennaShort)
+  It is a reverse biased diode whose leakage current will discharge the interconnect area.
+
+These devices are not subject to LVS check and must not be reported in the schematic.
+
+Antenna rules are defined for the following ratio:
+
+When a diode is used
+  ``EGAR``
+
+  Etch Gate Area Ratio = (EA / A_gate) - K x (AntennaDiode_area in um2) - diode_bonus [unitless]
+
+When diodes are not used
+  ``EGAR``
+
+  Etch Gate Area Ratio = (EA / A_gate)  [unitless]
+
+where:
+
+* ``K`` is a multiplying factor specified for each layer
+
+* ``AntennaDiode_area`` is the area of the AntennaDiode used to discharge the interconnect area exposed to plasma etch (should be 0 if no diode is used)
+
+The layout should satisfy the condition: ``EGAR`` <= ``MAX_EGAR``. The ``diode_bonus`` applies only when at least one diode is used, regardless from it's size.
+
+Tables
+------
+
+.. todo:: Most of these tables should be removed.
+
+
+.. csv-table:: Table Ia.  Antenna rules (S8D*)
+   :file: antenna/table-Ia-antenna-rules-s8d.csv
+   :header-rows: 1
+   :stub-columns: 1
+
+.. csv-table:: Table Ib. Antenna rules (S8TNV-5R)
+   :file: antenna/table-Ib-antenna-rules-s8tnv-5r.csv
+   :header-rows: 1
+   :stub-columns: 1
+
+.. csv-table:: Table Ic. Antenna rules (S8TM-5R*/S8TMC-5R*/S8TMA-5R*)
+   :file: antenna/table-Ic-antenna-rules-s8tm.csv
+   :header-rows: 1
+   :stub-columns: 1
+
+.. csv-table:: Table Ie. Antenna rules (S8P-5R/SP8P-5R/S8P-10R*)
+   :file: antenna/table-Ie-antenna-rules-s8p.csv
+   :header-rows: 1
+   :stub-columns: 1
+
+.. csv-table:: Table Ig. Antenna rules (S8P12-10R*/S8PIR-10R/S8PF-10R*)
+   :file: antenna/table-Ig-antenna-rules-s8p12.csv
+   :header-rows: 1
+   :stub-columns: 1

docs/rules/antenna/definitions.csv

@@ -0,0 +1,9 @@
+Symbol,Explanation,Unit
+PI,Perimeter of Interconnect,um
+FLT,Final Layer thickness,um
+W,Width of  MOS Transistor,um
+L,Length of  MOS Transistor,um
+A,Area of  MOS Transistor gate (= W x L),um2
+CA,Area of contact or via,um2
+SW,Sidewall area (= PI x FLT),um2
+EA,"Etched area (= CA for horizontal, = SW for vertical areas)",um2

docs/rules/antenna/table-Ia-antenna-rules-s8d.csv

@@ -0,0 +1,24 @@
+,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,,
+(ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus
+,,,,,,
+.poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a
+.licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a
+.li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a
+.mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a
+.met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200
+.via.1,Via (via area/gate area),Horizontal,,6,36,n/a
+.met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200
+.pad.1,pad (via2 area/gate area),Horizontal,,6,36,n/a
+.indm.1,INDM (met3 perimeter area/gate area),Vertical,4.000,400,400,2200
+.ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,,
+Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,,
+,,,,,,
+"Max length of Poly (approx, assumes min width)",,135,,n/a,,
+Max number of Licons,,103,,n/a,,
+"Max length of LI (approx, assumes min width)",,370,,2620,,
+Max number of Mcon,,103,,726,,
+"Max length of Met1 (approx, assumes min width)",,570,,4280,,
+Max number of Via,,266,,1866,,
+"Max length of Met2 (approx, assumes min width)",,570,,4280,,
+Max number of pad via,,4,,29,,
+"Max length of Met3 (approx, assumes min width)",,45,,370,,

docs/rules/antenna/table-Ib-antenna-rules-s8tnv-5r.csv

@@ -0,0 +1,25 @@
+Table Ib. Antenna rules (S8TNV-5R),,,,,,
+,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,,
+(ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus
+,,,,,,
+.poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a
+.licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a
+.li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a
+.mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a
+.met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200
+.via.1,Via (via area/gate area),Horizontal,,6,36,n/a
+.met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200
+.via2.1,Via2 (via2 area/gate area),Horizontal,,6,36,n/a
+.met3.1,Met3 (met3 perimeter area/gate area),Vertical,0.850,400,400,2200
+.ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,,
+Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,,
+,,,,,,
+"Max length of Poly (approx, assumes min width)",,135,,n/a,,
+Max number of Licons,,103,,n/a,,
+"Max length of LI (approx, assumes min width)",,370,,2620,,
+Max number of Mcon,,103,,726,,
+"Max length of Met1 (approx, assumes min width)",,570,,4280,,
+Max number of Via,,266,,1866,,
+"Max length of Met2 (approx, assumes min width)",,570,,4280,,
+Max number of Via2,,76,,535,,
+"Max length of Met3 (approx, assumes min width)",,230,,1760,,

docs/rules/antenna/table-Ic-antenna-rules-s8tm.csv

@@ -0,0 +1,25 @@
+Table Ic. Antenna rules (S8TM-5R*/S8TMC-5R*/S8TMA-5R*),,,,,,
+,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,,
+(ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus
+,,,,,,
+.poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a
+.licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a
+.li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a
+.mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a
+.met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200
+.via.1,Via (via area/gate area),Horizontal,,6,36,n/a
+.met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200
+.via2.1,Via2 (via2 area/gate area),Horizontal,,6,36,n/a
+.met3.1,Met3 (met3 perimeter area/gate area),Vertical,2.000,400,400,2200
+.ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,,
+Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,,
+,,,,,,
+"Max length of Poly (approx, assumes min width)",,135,,n/a,,
+Max number of Licons,,103,,n/a,,
+"Max length of LI (approx, assumes min width)",,370,,2620,,
+Max number of Mcon,,103,,726,,
+"Max length of Met1 (approx, assumes min width)",,570,,4280,,
+Max number of Via,,266,,1866,,
+"Max length of Met2 (approx, assumes min width)",,570,,4280,,
+Max number of Via2,,9,,65,,
+"Max length of Met3 (approx, assumes min width)",,95,,740,,

docs/rules/antenna/table-Ie-antenna-rules-s8p.csv

@@ -0,0 +1,33 @@
+Table Ie. Antenna rules (S8P-5R/SP8P-5R/S8P-10R*),,,,,,
+,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,,
+(ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus
+,,,,,,
+.poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a
+.licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a
+.li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a
+.mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a
+.met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200
+.via.1,Via (via area/gate area),Horizontal,,6,36,n/a
+.met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200
+.via2.1,Via2 (via2 area/gate area),Horizontal,,6,36,n/a
+.met3.1,Met3 (met3 perimeter area/gate area),Vertical,0.800,400,400,2200
+via3.1,Via3 (via3 area/gate area),Horizontal,,6,36,n/a
+met4.1,Met4 (met4 perimeter area/gate area),Vertical,0.800,400,400,2200
+via4.1,Via3 (via3 area/gate area),Horizontal,,6,36,n/a
+waffle_chip,Met4 (met4 perimeter area/gate area),Vertical,2.000,400,400,2200
+.ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,,
+Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,,
+,,,,,,
+"Max length of Poly (approx, assumes min width)",,135,,n/a,,
+Max number of Licons,,103,,n/a,,
+"Max length of LI (approx, assumes min width)",,370,,2620,,
+Max number of Mcon,,103,,726,,
+"Max length of Met1 (approx, assumes min width)",,570,,4280,,
+Max number of Via,,266,,1866,,
+"Max length of Met2 (approx, assumes min width)",,570,,4280,,
+Max number of Via2,,150,,1050,,
+"Max length of Met3 (approx, assumes min width)",,245,,1870,,
+Max number of Via3,,150,,1050,,
+"Max length of Met4 (approx, assumes min width)",,245,,1870,,
+Max number of Via4,,9,,65,,
+"Max length of Met5 (approx, assumes min width)",,95,,740,,

docs/rules/antenna/table-Ig-antenna-rules-s8p12.csv

@@ -0,0 +1,33 @@
+Table Ig. Antenna rules (S8P12-10R*/S8PIR-10R/S8PF-10R*),,,,,,
+,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,,
+(ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus
+,,,,,,
+.poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a
+.licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a
+.li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a
+.mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a
+.met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200
+.via.1,Via (via area/gate area),Horizontal,,6,36,n/a
+.met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200
+.via2.1,Via2 (via2 area/gate area),Horizontal,,6,36,n/a
+.met3.1,Met3 (met3 perimeter area/gate area),Vertical,0.800,400,400,2200
+via3.1,Via3 (via3 area/gate area),Horizontal,,6,36,n/a
+met4.1,Met4 (met4 perimeter area/gate area),Vertical,0.800,400,400,2200
+via4.1,Via3 (via3 area/gate area),Horizontal,,6,36,n/a
+met5.1,Met4 (met4 perimeter area/gate area),Vertical,1.200,400,400,2200
+.ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,,
+Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,,
+,,,,,,
+"Max length of Poly (approx, assumes min width)",,135,,n/a,,
+Max number of Licons,,103,,n/a,,
+"Max length of LI (approx, assumes min width)",,370,,2620,,
+Max number of Mcon,,103,,726,,
+"Max length of Met1 (approx, assumes min width)",,570,,4280,,
+Max number of Via,,266,,1866,,
+"Max length of Met2 (approx, assumes min width)",,570,,4280,,
+Max number of Via2,,150,,1050,,
+"Max length of Met3 (approx, assumes min width)",,245,,1870,,
+Max number of Via3,,150,,1050,,
+"Max length of Met4 (approx, assumes min width)",,245,,1870,,
+Max number of Via4,,9,,65,,
+"Max length of Met5 (approx, assumes min width)",,165,,1240,,

docs/rules/errors.rst

@@ -8,4 +8,5 @@ criteria for GDS data.
 .. csv-table:: Table - Error Messages
    :file: errors.csv
    :header-rows: 1
+   :stub-columns: 1
    :widths: 10, 10, 80