pkgs/cpu-vexriscv: don't error when source has no Verilog files

Downstream users such as tock-litex may patch the `src` attribute of
this derivation, and point to a customized repository which does not
contain any pre-built CPU HDL files yet. Use the `-f` flag to avoid
having `rm` error when it is invoked without any files to delete.

Signed-off-by: Leon Schuermann <leon@is.currently.online>

pkgs/pythondata-cpu-vexriscv/generated.nix

@@ -38,7 +38,10 @@ mkSbtDerivation rec {
     runHook preBuild
 
     # delete old CPU variant sources
-    rm pythondata_cpu_vexriscv/verilog/*.v
+    #
+    # Depending on the `src` attribute, these might have already been cleaned,
+    # use `-f` to avoid generating an error.
+    rm -f pythondata_cpu_vexriscv/verilog/*.v
 
     # rebuild all CPU variants
     make -C pythondata_cpu_vexriscv/verilog