Update mmio to check if Base Address is valid

Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>

chipsec/hal/mmio.py

@@ -22,32 +22,32 @@
 Access to MMIO (Memory Mapped IO) BARs and Memory-Mapped PCI Configuration Space (MMCFG)
 
 usage:
-    >>> read_MMIO_reg(cs, bar_base, 0x0, 4)
-    >>> write_MMIO_reg(cs, bar_base, 0x0, 0xFFFFFFFF, 4)
-    >>> read_MMIO(cs, bar_base, 0x1000)
-    >>> dump_MMIO(cs, bar_base, 0x1000)
+    >>> read_MMIO_reg(bar_base, 0x0, 4)
+    >>> write_MMIO_reg(bar_base, 0x0, 0xFFFFFFFF, 4)
+    >>> read_MMIO(bar_base, 0x1000)
+    >>> dump_MMIO(bar_base, 0x1000)
 
     Access MMIO by BAR name:
 
-    >>> read_MMIO_BAR_reg(cs, 'MCHBAR', 0x0, 4)
-    >>> write_MMIO_BAR_reg(cs, 'MCHBAR', 0x0, 0xFFFFFFFF, 4)
-    >>> get_MMIO_BAR_base_address(cs, 'MCHBAR')
-    >>> is_MMIO_BAR_enabled(cs, 'MCHBAR')
-    >>> is_MMIO_BAR_programmed(cs, 'MCHBAR')
-    >>> dump_MMIO_BAR(cs, 'MCHBAR')
-    >>> list_MMIO_BARs(cs)
+    >>> read_MMIO_BAR_reg('MCHBAR', 0x0, 4)
+    >>> write_MMIO_BAR_reg('MCHBAR', 0x0, 0xFFFFFFFF, 4)
+    >>> get_MMIO_BAR_base_address('MCHBAR')
+    >>> is_MMIO_BAR_enabled('MCHBAR')
+    >>> is_MMIO_BAR_programmed('MCHBAR')
+    >>> dump_MMIO_BAR('MCHBAR')
+    >>> list_MMIO_BARs()
 
     Access Memory Mapped Config Space:
 
-    >>> get_MMCFG_base_address(cs)
-    >>> read_mmcfg_reg(cs, 0, 0, 0, 0x10, 4)
-    >>> read_mmcfg_reg(cs, 0, 0, 0, 0x10, 4, 0xFFFFFFFF)
+    >>> get_MMCFG_base_address()
+    >>> read_mmcfg_reg(0, 0, 0, 0x10, 4)
+    >>> read_mmcfg_reg(0, 0, 0, 0x10, 4, 0xFFFFFFFF)
 """
 from typing import List, Optional, Tuple
 from chipsec.hal import hal_base
 from chipsec.library.exceptions import CSReadError
 from chipsec.library.logger import logger
-from chipsec.library.defines import get_bits
+from chipsec.library.defines import get_bits, is_all_ones
 
 DEFAULT_MMIO_BAR_SIZE = 0x1000
 
@@ -196,6 +196,7 @@ def get_MMIO_BAR_base_address(self, bar_name: str, bus: Optional[int] = None) ->
         _bus = bus
         limit = 0
 
+        is_ba_invalid = False
         if 'register' in bar:
             preserve = True
             bar_reg = bar['register']
@@ -211,6 +212,7 @@ def get_MMIO_BAR_base_address(self, bar_name: str, bus: Optional[int] = None) ->
                 except CSReadError:
                     base = 0
                     self.logger.log_hal(f'[mmio] Unable to determine MMIO Base.  Using Base = 0x{base:X}')
+                is_ba_invalid = base == 0 or self.cs.register.is_field_all_ones(bar_reg, base_field, base)
                 try:
                     reg_mask = self.cs.register.get_field_mask(bar_reg, base_field, preserve)
                 except CSReadError:
@@ -236,12 +238,14 @@ def get_MMIO_BAR_base_address(self, bar_name: str, bus: Optional[int] = None) ->
             r = bar['reg']
             width = bar['width']
             reg_mask = (1 << (width * 8)) - 1
+            size = 4 if width != 8 else 8
             if 8 == width:
                 base_lo = self.cs.pci.read_dword(b, d, f, r)
                 base_hi = self.cs.pci.read_dword(b, d, f, r + 4)
                 base = (base_hi << 32) | base_lo
             else:
                 base = self.cs.pci.read_dword(b, d, f, r)
+            is_ba_invalid = base == 0 or is_all_ones(base, size)
 
         if 'fixed_address' in bar and (base == reg_mask or base == 0):
             base = bar['fixed_address']
@@ -265,9 +269,9 @@ def get_MMIO_BAR_base_address(self, bar_name: str, bus: Optional[int] = None) ->
             size = bar['size'] if ('size' in bar) else DEFAULT_MMIO_BAR_SIZE
 
         self.logger.log_hal(f'[mmio] {bar_name}: 0x{base:016X} (size = 0x{size:X})')
-        if base == 0:
-            self.logger.log_hal('[mmio] Base address was determined to be 0.')
-            raise CSReadError('[mmio] Base address was determined to be 0')
+        if is_ba_invalid:
+            self.logger.log_hal('[mmio] Base address was determined to be invalid.')
+            raise CSReadError(f'[mmio] Base address was determined to be invalid: 0x{base:016X}')
 
         if self.cache_bar_addresses_resolution:
             self.cached_bar_addresses[(bar_name, bus)] = (base, size)

chipsec/modules/common/bios_ts.py

@@ -38,6 +38,7 @@
 
 """
 
+from chipsec.library.exceptions import CSReadError
 from chipsec.module_common import BaseModule, MTAG_BIOS
 from chipsec.library.returncode import ModuleResult
 from typing import List
@@ -86,5 +87,10 @@ def check_bios_iface_lock(self) -> int:
 
     def run(self, module_argv: List[str]) -> int:
         self.logger.start_test("BIOS Interface Lock (including Top Swap Mode)")
-        self.res = self.check_bios_iface_lock()
+        try:
+            self.res = self.check_bios_iface_lock()
+        except CSReadError as err:
+            self.logger.log_warning(f"Unable to read register: {err}")
+            self.result.setStatusBit(self.result.status.VERIFY)
+            self.res = self.result.getReturnCode(ModuleResult.WARNING)
         return self.res

chipsec/modules/common/bios_wp.py

@@ -57,6 +57,7 @@
 
 """
 
+from chipsec.library.exceptions import CSReadError
 from chipsec.module_common import BaseModule, MTAG_BIOS
 from chipsec.library.returncode import ModuleResult
 from chipsec.hal.spi import BIOS, SPI
@@ -70,7 +71,6 @@ class bios_wp(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.spi = SPI(self.cs)
 
     def is_supported(self) -> bool:
         ble_exists = self.cs.control.is_defined('BiosLockEnable')
@@ -155,8 +155,14 @@ def check_SPI_protected_ranges(self) -> bool:
 
     def run(self, module_argv: List[str]) -> int:
         self.logger.start_test("BIOS Region Write Protection")
-        wp = self.check_BIOS_write_protection()
-        spr = self.check_SPI_protected_ranges()
+        try:
+            self.spi = SPI(self.cs)
+            wp = self.check_BIOS_write_protection()
+            spr = self.check_SPI_protected_ranges()
+        except CSReadError as err:
+            self.logger.log_warning(f"Unable to read register: {err}")
+            self.result.setStatusBit(self.result.status.VERIFY)
+            return self.result.getReturnCode(ModuleResult.WARNING)
 
         self.logger.log('')
         if wp:

chipsec/modules/common/spi_access.py

@@ -45,6 +45,7 @@
 
 """
 
+from chipsec.library.exceptions import CSReadError
 from chipsec.module_common import BaseModule, MTAG_BIOS
 from chipsec.library.returncode import ModuleResult
 from chipsec.hal.spi import SPI, GBE, PLATFORM_DATA, ME, FLASH_DESCRIPTOR
@@ -57,7 +58,6 @@ class spi_access(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.spi = SPI(self.cs)
 
     def is_supported(self) -> bool:
         if self.cs.register.has_field('HSFS', 'FDV') and self.cs.register.has_field('FRAP', 'BRWA'):
@@ -121,6 +121,12 @@ def check_flash_access_permissions(self) -> int:
 
     def run(self, module_argv: List[str]) -> int:
         self.logger.start_test("SPI Flash Region Access Control")
-        self.spi.display_SPI_Ranges_Access_Permissions()
-        self.res = self.check_flash_access_permissions()
+        try:
+            self.spi = SPI(self.cs)
+            self.spi.display_SPI_Ranges_Access_Permissions()
+            self.res = self.check_flash_access_permissions()
+        except CSReadError as err:
+            self.logger.log_warning(f"Unable to read register: {err}")
+            self.result.setStatusBit(self.result.status.VERIFY)
+            self.res = self.result.getReturnCode(ModuleResult.WARNING)
         return self.res

chipsec/modules/common/spi_desc.py

@@ -39,6 +39,7 @@
 
 """
 
+from chipsec.library.exceptions import CSReadError
 from chipsec.module_common import BaseModule, MTAG_BIOS
 from chipsec.library.returncode import ModuleResult
 from chipsec.hal.spi import FLASH_DESCRIPTOR
@@ -85,5 +86,10 @@ def check_flash_access_permissions(self) -> int:
 
     def run(self, module_argv: List[str]) -> int:
         self.logger.start_test("SPI Flash Region Access Control")
-        self.res = self.check_flash_access_permissions()
+        try:
+            self.res = self.check_flash_access_permissions()
+        except CSReadError as err:
+            self.logger.log_warning(f"Unable to read register: {err}")
+            self.result.setStatusBit(self.result.status.VERIFY)
+            self.res = self.result.getReturnCode(ModuleResult.WARNING)
         return self.res

chipsec/modules/common/spi_fdopss.py

@@ -33,6 +33,7 @@
 
 """
 
+from chipsec.library.exceptions import CSReadError
 from chipsec.module_common import BaseModule, MTAG_BIOS
 from chipsec.library.returncode import ModuleResult
 from typing import List
@@ -70,5 +71,10 @@ def check_fd_security_override_strap(self) -> int:
     # --------------------------------------------------------------------------
     def run(self, module_argv: List[str]) -> int:
         self.logger.start_test("SPI Flash Descriptor Security Override Pin-Strap")
-        self.res = self.check_fd_security_override_strap()
+        try:
+            self.res = self.check_fd_security_override_strap()
+        except CSReadError as err:
+            self.logger.log_warning(f"Unable to read register: {err}")
+            self.result.setStatusBit(self.result.status.VERIFY)
+            self.res = self.result.getReturnCode(ModuleResult.WARNING)
         return self.res

chipsec/modules/common/spi_lock.py

@@ -43,6 +43,7 @@
 
 """
 
+from chipsec.library.exceptions import CSReadError
 from chipsec.module_common import BaseModule, MTAG_BIOS
 from chipsec.library.returncode import ModuleResult
 from typing import List
@@ -94,5 +95,10 @@ def check_spi_lock(self) -> int:
 
     def run(self, module_argv: List[str]) -> int:
         self.logger.start_test("SPI Flash Controller Configuration Locks")
-        self.res = self.check_spi_lock()
+        try:
+            self.res = self.check_spi_lock()
+        except CSReadError as err:
+            self.logger.log_warning(f"Unable to read register: {err}")
+            self.result.setStatusBit(self.result.status.VERIFY)
+            self.res = self.result.getReturnCode(ModuleResult.WARNING)
         return self.res