GitHub - pahanmendis/BCD-to-7-SEGMENT-using-Verilog-: This repository contains verilog code used to implment a BCD to 7 segment display. This implementation is done using gate level modeling as well as behavioral modelling.

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This repository contains verilog code used to implment a BCD to 7 segment display. This implementation is done using gate level modeling as well as behavioral modelling.

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.gitattributes		.gitattributes
DE10_LITE_TOP.v		DE10_LITE_TOP.v
bcd7segment.v		bcd7segment.v
bcd7segmentBehavioral.v		bcd7segmentBehavioral.v

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This repository contains verilog code used to implment a BCD to 7 segment display. This implementation is done using gate level modeling as well as behavioral modelling.

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