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occamy: Make generation script more flexible (#138)
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@zarubaf
zarubaf committed May 22, 2021
1 parent cc64926 commit 65fbbf6
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Showing 8 changed files with 249 additions and 216 deletions.
20 changes: 12 additions & 8 deletions hw/system/occamy/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -43,14 +43,18 @@ test/bootrom.elf test/bootrom.dump test/bootrom.bin: test/bootrom.S test/bootrom
##########
update-source:
@echo "[SOLDER] Generating sources"
@$(ROOT)/util/occamygen.py --cfg src/occamy_cfg.hjson --graph addrmap.dot --outdir . \
--dts test/occamy.dts \
src/occamy_top.sv \
src/occamy_pkg.sv \
src/occamy_quadrant_s1.sv \
src/occamy_xilinx.sv \
test/testharness.sv \
src/occamy_cva6.sv
@echo "[SOLDER] RTL"
@$(ROOT)/util/occamygen.py --cfg src/occamy_cfg.hjson --graph addrmap.dot --outdir src --wrapper --memories \
--top-sv src/occamy_top.sv.tpl \
--pkg-sv src/occamy_pkg.sv.tpl \
--quadrant-s1 src/occamy_quadrant_s1.sv.tpl \
--xilinx-sv src/occamy_xilinx.sv.tpl \
--cva6-sv src/occamy_cva6.sv.tpl
@echo "[SOLDER] Testbench"
@$(ROOT)/util/occamygen.py --cfg src/occamy_cfg.hjson --graph addrmap.dot --outdir test \
--testharness-sv test/testharness.sv.tpl
@echo "[SOLDER] Device Tree"
@$(ROOT)/util/occamygen.py --cfg src/occamy_cfg.hjson --outdir . --dts test/occamy.dts
@echo "[VERIBLE] Formatting"
@verible-verilog-format --inplace src/occamy_quadrant_s1.sv src/occamy_pkg.sv src/occamy_top.sv src/occamy_xilinx.sv src/occamy_cva6.sv

Expand Down
148 changes: 75 additions & 73 deletions hw/system/occamy/src/occamy_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -98,23 +98,23 @@ package occamy_pkg;

/// Configuration of the `soc_axi_lite_periph_xbar` crossbar.
localparam axi_pkg::xbar_cfg_t SocAxiLitePeriphXbarCfg = '{
NoSlvPorts: SOC_AXI_LITE_PERIPH_XBAR_NUM_INPUTS,
NoMstPorts: SOC_AXI_LITE_PERIPH_XBAR_NUM_OUTPUTS,
MaxSlvTrans: 4,
MaxMstTrans: 4,
FallThrough: 0,
LatencyMode: axi_pkg::CUT_ALL_PORTS,
AxiIdWidthSlvPorts: 0,
AxiIdUsedSlvPorts: 0,
AxiAddrWidth: 48,
AxiDataWidth: 64,
NoAddrRules: 1
};
NoSlvPorts: SOC_AXI_LITE_PERIPH_XBAR_NUM_INPUTS,
NoMstPorts: SOC_AXI_LITE_PERIPH_XBAR_NUM_OUTPUTS,
MaxSlvTrans: 4,
MaxMstTrans: 4,
FallThrough: 0,
LatencyMode: axi_pkg::CUT_ALL_PORTS,
AxiIdWidthSlvPorts: 0,
AxiIdUsedSlvPorts: 0,
AxiAddrWidth: 48,
AxiDataWidth: 64,
NoAddrRules: 1
};

/// Address map of the `soc_axi_lite_periph_xbar` crossbar.
localparam xbar_rule_48_t [0:0] SocAxiLitePeriphXbarAddrmap = '{
'{ idx: 0, start_addr: 48'h00000000, end_addr: 48'h00001000 }
};
'{ idx: 0, start_addr: 48'h00000000, end_addr: 48'h00001000 }
};

// AXI plugs of the `soc_axi_lite_periph_xbar` crossbar.

Expand Down Expand Up @@ -153,21 +153,23 @@ package occamy_pkg;
SOC_REGBUS_PERIPH_XBAR_OUT_GPIO,
SOC_REGBUS_PERIPH_XBAR_OUT_I2C,
SOC_REGBUS_PERIPH_XBAR_OUT_SPIM,
SOC_REGBUS_PERIPH_XBAR_OUT_PCIE_CFG,
SOC_REGBUS_PERIPH_XBAR_NUM_OUTPUTS
} soc_regbus_periph_xbar_outputs_e;

/// Address map of the `soc_regbus_periph_xbar` crossbar.
localparam xbar_rule_48_t [8:0] SocRegbusPeriphXbarAddrmap = '{
'{ idx: 0, start_addr: 48'h04000000, end_addr: 48'h04100000 },
'{ idx: 1, start_addr: 48'h02000000, end_addr: 48'h02001000 },
'{ idx: 2, start_addr: 48'h02001000, end_addr: 48'h02002000 },
'{ idx: 3, start_addr: 48'h01000000, end_addr: 48'h01020000 },
'{ idx: 4, start_addr: 48'h0c000000, end_addr: 48'h10000000 },
'{ idx: 5, start_addr: 48'h02002000, end_addr: 48'h02003000 },
'{ idx: 6, start_addr: 48'h02003000, end_addr: 48'h02004000 },
'{ idx: 7, start_addr: 48'h02004000, end_addr: 48'h02005000 },
'{ idx: 8, start_addr: 48'h03000000, end_addr: 48'h03020000 }
};
localparam xbar_rule_48_t [9:0] SocRegbusPeriphXbarAddrmap = '{
'{ idx: 0, start_addr: 48'h04000000, end_addr: 48'h04100000 },
'{ idx: 1, start_addr: 48'h02000000, end_addr: 48'h02001000 },
'{ idx: 2, start_addr: 48'h02001000, end_addr: 48'h02002000 },
'{ idx: 3, start_addr: 48'h01000000, end_addr: 48'h01020000 },
'{ idx: 4, start_addr: 48'h0c000000, end_addr: 48'h10000000 },
'{ idx: 5, start_addr: 48'h02002000, end_addr: 48'h02003000 },
'{ idx: 6, start_addr: 48'h02003000, end_addr: 48'h02004000 },
'{ idx: 7, start_addr: 48'h02004000, end_addr: 48'h02005000 },
'{ idx: 8, start_addr: 48'h03000000, end_addr: 48'h03020000 },
'{ idx: 9, start_addr: 48'h05000000, end_addr: 48'h05020000 }
};

/// Inputs of the `soc_wide_xbar` crossbar.
typedef enum int {
Expand Down Expand Up @@ -216,18 +218,18 @@ package occamy_pkg;

/// Configuration of the `soc_wide_xbar` crossbar.
localparam axi_pkg::xbar_cfg_t SocWideXbarCfg = '{
NoSlvPorts: SOC_WIDE_XBAR_NUM_INPUTS,
NoMstPorts: SOC_WIDE_XBAR_NUM_OUTPUTS,
MaxSlvTrans: 4,
MaxMstTrans: 4,
FallThrough: 0,
LatencyMode: axi_pkg::CUT_ALL_PORTS,
AxiIdWidthSlvPorts: 3,
AxiIdUsedSlvPorts: 3,
AxiAddrWidth: 48,
AxiDataWidth: 512,
NoAddrRules: 19
};
NoSlvPorts: SOC_WIDE_XBAR_NUM_INPUTS,
NoMstPorts: SOC_WIDE_XBAR_NUM_OUTPUTS,
MaxSlvTrans: 4,
MaxMstTrans: 4,
FallThrough: 0,
LatencyMode: axi_pkg::CUT_ALL_PORTS,
AxiIdWidthSlvPorts: 3,
AxiIdUsedSlvPorts: 3,
AxiAddrWidth: 48,
AxiDataWidth: 512,
NoAddrRules: 19
};

// AXI bus with 48 bit address, 512 bit data, 3 bit IDs, and 0 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d512_i3_u0, logic [47:0], logic [2:0], logic [511:0], logic [63:0],
Expand Down Expand Up @@ -290,18 +292,18 @@ package occamy_pkg;

/// Configuration of the `soc_narrow_xbar` crossbar.
localparam axi_pkg::xbar_cfg_t SocNarrowXbarCfg = '{
NoSlvPorts: SOC_NARROW_XBAR_NUM_INPUTS,
NoMstPorts: SOC_NARROW_XBAR_NUM_OUTPUTS,
MaxSlvTrans: 4,
MaxMstTrans: 4,
FallThrough: 0,
LatencyMode: axi_pkg::CUT_ALL_PORTS,
AxiIdWidthSlvPorts: 4,
AxiIdUsedSlvPorts: 4,
AxiAddrWidth: 48,
AxiDataWidth: 64,
NoAddrRules: 13
};
NoSlvPorts: SOC_NARROW_XBAR_NUM_INPUTS,
NoMstPorts: SOC_NARROW_XBAR_NUM_OUTPUTS,
MaxSlvTrans: 4,
MaxMstTrans: 4,
FallThrough: 0,
LatencyMode: axi_pkg::CUT_ALL_PORTS,
AxiIdWidthSlvPorts: 4,
AxiIdUsedSlvPorts: 4,
AxiAddrWidth: 48,
AxiDataWidth: 64,
NoAddrRules: 13
};

// AXI bus with 48 bit address, 64 bit data, 4 bit IDs, and 0 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d64_i4_u0, logic [47:0], logic [3:0], logic [63:0], logic [7:0],
Expand Down Expand Up @@ -353,18 +355,18 @@ package occamy_pkg;

/// Configuration of the `wide_xbar_quadrant_s1` crossbar.
localparam axi_pkg::xbar_cfg_t WideXbarQuadrantS1Cfg = '{
NoSlvPorts: WIDE_XBAR_QUADRANT_S1_NUM_INPUTS,
NoMstPorts: WIDE_XBAR_QUADRANT_S1_NUM_OUTPUTS,
MaxSlvTrans: 4,
MaxMstTrans: 4,
FallThrough: 0,
LatencyMode: axi_pkg::CUT_ALL_PORTS,
AxiIdWidthSlvPorts: 3,
AxiIdUsedSlvPorts: 3,
AxiAddrWidth: 48,
AxiDataWidth: 512,
NoAddrRules: 4
};
NoSlvPorts: WIDE_XBAR_QUADRANT_S1_NUM_INPUTS,
NoMstPorts: WIDE_XBAR_QUADRANT_S1_NUM_OUTPUTS,
MaxSlvTrans: 4,
MaxMstTrans: 4,
FallThrough: 0,
LatencyMode: axi_pkg::CUT_ALL_PORTS,
AxiIdWidthSlvPorts: 3,
AxiIdUsedSlvPorts: 3,
AxiAddrWidth: 48,
AxiDataWidth: 512,
NoAddrRules: 4
};

// AXI bus with 48 bit address, 512 bit data, 6 bit IDs, and 0 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d512_i6_u0, logic [47:0], logic [5:0], logic [511:0], logic [63:0],
Expand Down Expand Up @@ -412,18 +414,18 @@ package occamy_pkg;

/// Configuration of the `narrow_xbar_quadrant_s1` crossbar.
localparam axi_pkg::xbar_cfg_t NarrowXbarQuadrantS1Cfg = '{
NoSlvPorts: NARROW_XBAR_QUADRANT_S1_NUM_INPUTS,
NoMstPorts: NARROW_XBAR_QUADRANT_S1_NUM_OUTPUTS,
MaxSlvTrans: 4,
MaxMstTrans: 4,
FallThrough: 0,
LatencyMode: axi_pkg::CUT_ALL_PORTS,
AxiIdWidthSlvPorts: 4,
AxiIdUsedSlvPorts: 4,
AxiAddrWidth: 48,
AxiDataWidth: 64,
NoAddrRules: 4
};
NoSlvPorts: NARROW_XBAR_QUADRANT_S1_NUM_INPUTS,
NoMstPorts: NARROW_XBAR_QUADRANT_S1_NUM_OUTPUTS,
MaxSlvTrans: 4,
MaxMstTrans: 4,
FallThrough: 0,
LatencyMode: axi_pkg::CUT_ALL_PORTS,
AxiIdWidthSlvPorts: 4,
AxiIdUsedSlvPorts: 4,
AxiAddrWidth: 48,
AxiDataWidth: 64,
NoAddrRules: 4
};

// AXI bus with 48 bit address, 64 bit data, 7 bit IDs, and 0 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d64_i7_u0, logic [47:0], logic [6:0], logic [63:0], logic [7:0],
Expand Down
20 changes: 10 additions & 10 deletions hw/system/occamy/src/occamy_quadrant_s1.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -43,11 +43,11 @@ module occamy_quadrant_s1
/// Address map of the `wide_xbar_quadrant_s1` crossbar.
xbar_rule_48_t [3:0] WideXbarQuadrantS1Addrmap;
assign WideXbarQuadrantS1Addrmap = '{
'{ idx: 1, start_addr: cluster_base_addr[0], end_addr: cluster_base_addr[0] + ClusterAddressSpace },
'{ idx: 2, start_addr: cluster_base_addr[1], end_addr: cluster_base_addr[1] + ClusterAddressSpace },
'{ idx: 3, start_addr: cluster_base_addr[2], end_addr: cluster_base_addr[2] + ClusterAddressSpace },
'{ idx: 4, start_addr: cluster_base_addr[3], end_addr: cluster_base_addr[3] + ClusterAddressSpace }
};
'{ idx: 1, start_addr: cluster_base_addr[0], end_addr: cluster_base_addr[0] + ClusterAddressSpace },
'{ idx: 2, start_addr: cluster_base_addr[1], end_addr: cluster_base_addr[1] + ClusterAddressSpace },
'{ idx: 3, start_addr: cluster_base_addr[2], end_addr: cluster_base_addr[2] + ClusterAddressSpace },
'{ idx: 4, start_addr: cluster_base_addr[3], end_addr: cluster_base_addr[3] + ClusterAddressSpace }
};

wide_xbar_quadrant_s1_in_req_t [4:0] wide_xbar_quadrant_s1_in_req;
wide_xbar_quadrant_s1_in_resp_t [4:0] wide_xbar_quadrant_s1_in_rsp;
Expand Down Expand Up @@ -87,11 +87,11 @@ module occamy_quadrant_s1
/// Address map of the `narrow_xbar_quadrant_s1` crossbar.
xbar_rule_48_t [3:0] NarrowXbarQuadrantS1Addrmap;
assign NarrowXbarQuadrantS1Addrmap = '{
'{ idx: 1, start_addr: cluster_base_addr[0], end_addr: cluster_base_addr[0] + ClusterAddressSpace },
'{ idx: 2, start_addr: cluster_base_addr[1], end_addr: cluster_base_addr[1] + ClusterAddressSpace },
'{ idx: 3, start_addr: cluster_base_addr[2], end_addr: cluster_base_addr[2] + ClusterAddressSpace },
'{ idx: 4, start_addr: cluster_base_addr[3], end_addr: cluster_base_addr[3] + ClusterAddressSpace }
};
'{ idx: 1, start_addr: cluster_base_addr[0], end_addr: cluster_base_addr[0] + ClusterAddressSpace },
'{ idx: 2, start_addr: cluster_base_addr[1], end_addr: cluster_base_addr[1] + ClusterAddressSpace },
'{ idx: 3, start_addr: cluster_base_addr[2], end_addr: cluster_base_addr[2] + ClusterAddressSpace },
'{ idx: 4, start_addr: cluster_base_addr[3], end_addr: cluster_base_addr[3] + ClusterAddressSpace }
};

narrow_xbar_quadrant_s1_in_req_t [4:0] narrow_xbar_quadrant_s1_in_req;
narrow_xbar_quadrant_s1_in_resp_t [4:0] narrow_xbar_quadrant_s1_in_rsp;
Expand Down
78 changes: 41 additions & 37 deletions hw/system/occamy/src/occamy_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,10 @@ module occamy_top
output reg_a48_d32_req_t clk_mgr_req_o,
input reg_a48_d32_rsp_t clk_mgr_rsp_i,

/// PCIe/DDR Config
output reg_a48_d32_req_t pcie_cfg_req_o,
input reg_a48_d32_rsp_t pcie_cfg_rsp_i,

// "external interrupts from uncore - "programmable"
input logic [3:0] ext_irq_i,

Expand Down Expand Up @@ -168,8 +172,8 @@ module occamy_top

reg_a48_d32_req_t [0:0] soc_regbus_periph_xbar_in_req;
reg_a48_d32_rsp_t [0:0] soc_regbus_periph_xbar_in_rsp;
reg_a48_d32_req_t [8:0] soc_regbus_periph_xbar_out_req;
reg_a48_d32_rsp_t [8:0] soc_regbus_periph_xbar_out_rsp;
reg_a48_d32_req_t [9:0] soc_regbus_periph_xbar_out_req;
reg_a48_d32_rsp_t [9:0] soc_regbus_periph_xbar_out_rsp;

logic [cf_math_pkg::idx_width(
SOC_REGBUS_PERIPH_XBAR_NUM_OUTPUTS
Expand All @@ -192,7 +196,7 @@ SOC_REGBUS_PERIPH_XBAR_NUM_OUTPUTS

addr_decode #(
.NoIndices(SOC_REGBUS_PERIPH_XBAR_NUM_OUTPUTS),
.NoRules(9),
.NoRules(10),
.addr_t(logic [47:0]),
.rule_t(xbar_rule_48_t)
) i_addr_decode_soc_regbus_periph_xbar (
Expand All @@ -208,26 +212,26 @@ SOC_REGBUS_PERIPH_XBAR_NUM_OUTPUTS
/// Address map of the `soc_wide_xbar` crossbar.
xbar_rule_48_t [18:0] SocWideXbarAddrmap;
assign SocWideXbarAddrmap = '{
'{ idx: 8, start_addr: 48'h80000000, end_addr: 48'hc0000000 },
'{ idx: 8, start_addr: 48'h1000000000, end_addr: 48'h1040000000 },
'{ idx: 9, start_addr: 48'hc0000000, end_addr: 48'h100000000 },
'{ idx: 9, start_addr: 48'h1040000000, end_addr: 48'h1080000000 },
'{ idx: 10, start_addr: 48'h1080000000, end_addr: 48'h10c0000000 },
'{ idx: 11, start_addr: 48'h10c0000000, end_addr: 48'h1100000000 },
'{ idx: 12, start_addr: 48'h1100000000, end_addr: 48'h1140000000 },
'{ idx: 13, start_addr: 48'h1140000000, end_addr: 48'h1180000000 },
'{ idx: 14, start_addr: 48'h1180000000, end_addr: 48'h11c0000000 },
'{ idx: 15, start_addr: 48'h11c0000000, end_addr: 48'h1200000000 },
'{ idx: 16, start_addr: 48'h20000000, end_addr: 48'h70000000 },
'{ idx: 0, start_addr: s1_quadrant_base_addr[0], end_addr: s1_quadrant_base_addr[0] + S1QuadrantAddressSpace },
'{ idx: 1, start_addr: s1_quadrant_base_addr[1], end_addr: s1_quadrant_base_addr[1] + S1QuadrantAddressSpace },
'{ idx: 2, start_addr: s1_quadrant_base_addr[2], end_addr: s1_quadrant_base_addr[2] + S1QuadrantAddressSpace },
'{ idx: 3, start_addr: s1_quadrant_base_addr[3], end_addr: s1_quadrant_base_addr[3] + S1QuadrantAddressSpace },
'{ idx: 4, start_addr: s1_quadrant_base_addr[4], end_addr: s1_quadrant_base_addr[4] + S1QuadrantAddressSpace },
'{ idx: 5, start_addr: s1_quadrant_base_addr[5], end_addr: s1_quadrant_base_addr[5] + S1QuadrantAddressSpace },
'{ idx: 6, start_addr: s1_quadrant_base_addr[6], end_addr: s1_quadrant_base_addr[6] + S1QuadrantAddressSpace },
'{ idx: 7, start_addr: s1_quadrant_base_addr[7], end_addr: s1_quadrant_base_addr[7] + S1QuadrantAddressSpace }
};
'{ idx: 8, start_addr: 48'h80000000, end_addr: 48'hc0000000 },
'{ idx: 8, start_addr: 48'h1000000000, end_addr: 48'h1040000000 },
'{ idx: 9, start_addr: 48'hc0000000, end_addr: 48'h100000000 },
'{ idx: 9, start_addr: 48'h1040000000, end_addr: 48'h1080000000 },
'{ idx: 10, start_addr: 48'h1080000000, end_addr: 48'h10c0000000 },
'{ idx: 11, start_addr: 48'h10c0000000, end_addr: 48'h1100000000 },
'{ idx: 12, start_addr: 48'h1100000000, end_addr: 48'h1140000000 },
'{ idx: 13, start_addr: 48'h1140000000, end_addr: 48'h1180000000 },
'{ idx: 14, start_addr: 48'h1180000000, end_addr: 48'h11c0000000 },
'{ idx: 15, start_addr: 48'h11c0000000, end_addr: 48'h1200000000 },
'{ idx: 16, start_addr: 48'h20000000, end_addr: 48'h70000000 },
'{ idx: 0, start_addr: s1_quadrant_base_addr[0], end_addr: s1_quadrant_base_addr[0] + S1QuadrantAddressSpace },
'{ idx: 1, start_addr: s1_quadrant_base_addr[1], end_addr: s1_quadrant_base_addr[1] + S1QuadrantAddressSpace },
'{ idx: 2, start_addr: s1_quadrant_base_addr[2], end_addr: s1_quadrant_base_addr[2] + S1QuadrantAddressSpace },
'{ idx: 3, start_addr: s1_quadrant_base_addr[3], end_addr: s1_quadrant_base_addr[3] + S1QuadrantAddressSpace },
'{ idx: 4, start_addr: s1_quadrant_base_addr[4], end_addr: s1_quadrant_base_addr[4] + S1QuadrantAddressSpace },
'{ idx: 5, start_addr: s1_quadrant_base_addr[5], end_addr: s1_quadrant_base_addr[5] + S1QuadrantAddressSpace },
'{ idx: 6, start_addr: s1_quadrant_base_addr[6], end_addr: s1_quadrant_base_addr[6] + S1QuadrantAddressSpace },
'{ idx: 7, start_addr: s1_quadrant_base_addr[7], end_addr: s1_quadrant_base_addr[7] + S1QuadrantAddressSpace }
};

soc_wide_xbar_in_req_t [17:0] soc_wide_xbar_in_req;
soc_wide_xbar_in_resp_t [17:0] soc_wide_xbar_in_rsp;
Expand Down Expand Up @@ -267,20 +271,20 @@ SOC_REGBUS_PERIPH_XBAR_NUM_OUTPUTS
/// Address map of the `soc_narrow_xbar` crossbar.
xbar_rule_48_t [12:0] SocNarrowXbarAddrmap;
assign SocNarrowXbarAddrmap = '{
'{ idx: 8, start_addr: 48'h00000000, end_addr: 48'h00001000 },
'{ idx: 9, start_addr: 48'h70000000, end_addr: 48'h80000000 },
'{ idx: 10, start_addr: 48'h20000000, end_addr: 48'h70000000 },
'{ idx: 10, start_addr: 48'h80000000, end_addr: 48'h1200000000 },
'{ idx: 11, start_addr: 48'h01000000, end_addr: 48'h10000000 },
'{ idx: 0, start_addr: s1_quadrant_base_addr[0], end_addr: s1_quadrant_base_addr[0] + S1QuadrantAddressSpace },
'{ idx: 1, start_addr: s1_quadrant_base_addr[1], end_addr: s1_quadrant_base_addr[1] + S1QuadrantAddressSpace },
'{ idx: 2, start_addr: s1_quadrant_base_addr[2], end_addr: s1_quadrant_base_addr[2] + S1QuadrantAddressSpace },
'{ idx: 3, start_addr: s1_quadrant_base_addr[3], end_addr: s1_quadrant_base_addr[3] + S1QuadrantAddressSpace },
'{ idx: 4, start_addr: s1_quadrant_base_addr[4], end_addr: s1_quadrant_base_addr[4] + S1QuadrantAddressSpace },
'{ idx: 5, start_addr: s1_quadrant_base_addr[5], end_addr: s1_quadrant_base_addr[5] + S1QuadrantAddressSpace },
'{ idx: 6, start_addr: s1_quadrant_base_addr[6], end_addr: s1_quadrant_base_addr[6] + S1QuadrantAddressSpace },
'{ idx: 7, start_addr: s1_quadrant_base_addr[7], end_addr: s1_quadrant_base_addr[7] + S1QuadrantAddressSpace }
};
'{ idx: 8, start_addr: 48'h00000000, end_addr: 48'h00001000 },
'{ idx: 9, start_addr: 48'h70000000, end_addr: 48'h80000000 },
'{ idx: 10, start_addr: 48'h20000000, end_addr: 48'h70000000 },
'{ idx: 10, start_addr: 48'h80000000, end_addr: 48'h1200000000 },
'{ idx: 11, start_addr: 48'h01000000, end_addr: 48'h10000000 },
'{ idx: 0, start_addr: s1_quadrant_base_addr[0], end_addr: s1_quadrant_base_addr[0] + S1QuadrantAddressSpace },
'{ idx: 1, start_addr: s1_quadrant_base_addr[1], end_addr: s1_quadrant_base_addr[1] + S1QuadrantAddressSpace },
'{ idx: 2, start_addr: s1_quadrant_base_addr[2], end_addr: s1_quadrant_base_addr[2] + S1QuadrantAddressSpace },
'{ idx: 3, start_addr: s1_quadrant_base_addr[3], end_addr: s1_quadrant_base_addr[3] + S1QuadrantAddressSpace },
'{ idx: 4, start_addr: s1_quadrant_base_addr[4], end_addr: s1_quadrant_base_addr[4] + S1QuadrantAddressSpace },
'{ idx: 5, start_addr: s1_quadrant_base_addr[5], end_addr: s1_quadrant_base_addr[5] + S1QuadrantAddressSpace },
'{ idx: 6, start_addr: s1_quadrant_base_addr[6], end_addr: s1_quadrant_base_addr[6] + S1QuadrantAddressSpace },
'{ idx: 7, start_addr: s1_quadrant_base_addr[7], end_addr: s1_quadrant_base_addr[7] + S1QuadrantAddressSpace }
};

soc_narrow_xbar_in_req_t [ 8:0] soc_narrow_xbar_in_req;
soc_narrow_xbar_in_resp_t [ 8:0] soc_narrow_xbar_in_rsp;
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4 changes: 4 additions & 0 deletions hw/system/occamy/src/occamy_top.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,10 @@ module occamy_top
output ${soc_regbus_periph_xbar.out_clk_mgr.req_type()} clk_mgr_req_o,
input ${soc_regbus_periph_xbar.out_clk_mgr.rsp_type()} clk_mgr_rsp_i,

/// PCIe/DDR Config
output ${soc_regbus_periph_xbar.out_pcie_cfg.req_type()} pcie_cfg_req_o,
input ${soc_regbus_periph_xbar.out_pcie_cfg.rsp_type()} pcie_cfg_rsp_i,

// "external interrupts from uncore - "programmable"
input logic [3:0] ext_irq_i,

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10 changes: 6 additions & 4 deletions hw/system/occamy/src/occamy_xilinx.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -608,10 +608,12 @@ module occamy_xilinx

// Occamy top-level
occamy_top i_occamy (
.bootrom_req_o(bootrom_req),
.bootrom_rsp_i(bootrom_rsp),
.clk_mgr_req_o(clk_mgr_req),
.clk_mgr_rsp_i(clk_mgr_rsp),
.bootrom_req_o (bootrom_req),
.bootrom_rsp_i (bootrom_rsp),
.clk_mgr_req_o (clk_mgr_req),
.clk_mgr_rsp_i (clk_mgr_rsp),
.pcie_cfg_req_o(),
.pcie_cfg_rsp_i('0),
.*
);

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