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hw: Add VFCVT(U).D.S instructions #170

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hw: Add VFCVT(U).D.S instructions #170

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2 changes: 2 additions & 0 deletions hw/snitch/src/riscv_instr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -704,6 +704,8 @@ package riscv_instr;
localparam logic [31:0] VFCVTU_S_B = 32'b100110000111?????100?????0110011;
localparam logic [31:0] VFCVT_B_S = 32'b100110000100?????011?????0110011;
localparam logic [31:0] VFCVTU_B_S = 32'b100110000100?????111?????0110011;
localparam logic [31:0] VFCVT_D_S = 32'b100110000100?????001?????0110011;
localparam logic [31:0] VFCVTU_D_S = 32'b100110000100?????101?????0110011;
localparam logic [31:0] VFCVT_H_B = 32'b100110000111?????010?????0110011;
localparam logic [31:0] VFCVTU_H_B = 32'b100110000111?????110?????0110011;
localparam logic [31:0] VFCVT_B_H = 32'b100110000110?????011?????0110011;
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13 changes: 13 additions & 0 deletions hw/snitch/src/snitch.sv
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Expand Up @@ -1354,6 +1354,19 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
illegal_inst = 1'b1;
end
end
VFCVT_D_S,
VFCVTU_D_S: begin
if (FP_EN && XFVEC && RVF && FLEN >= 32) begin
if (RVF && RVD) begin
write_rd = 1'b0;
acc_qvalid_o = valid_instr;
end else begin
illegal_inst = 1'b1;
end
end else begin
illegal_inst = 1'b1;
end
end
VFCVT_S_H,
VFCVTU_S_H: begin
if (FP_EN && XFVEC && RVF && FLEN >= 32) begin
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10 changes: 10 additions & 0 deletions hw/snitch_cluster/src/snitch_fp_ss.sv
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Expand Up @@ -528,6 +528,16 @@ module snitch_fp_ss import snitch_pkg::*; #(
vectorial_op = 1'b1;
set_dyn_rm = 1'b1;
end
riscv_instr::VFCVT_D_S,
riscv_instr::VFCVTU_D_S: begin
fpu_op = fpnew_pkg::F2F;
op_select[0] = RegA;
src_fmt = fpnew_pkg::FP32;
dst_fmt = fpnew_pkg::FP64;
vectorial_op = 1'b1;
set_dyn_rm = 1'b1;
if (acc_req_q.data_op inside {riscv_instr::VFCVTU_D_S}) op_mode = 1'b1;
end
// Double Precision
riscv_instr::FADD_D: begin
fpu_op = fpnew_pkg::ADD;
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