Skip to content

Issues: riscv-software-src/riscv-isa-sim

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

264 Open 572 Closed
264 Open 572 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

How to forcefully inject the rtl values into spike
#1809 opened Sep 16, 2024 by IMVelige
1
Clarification on VMSEQ Instruction Behavior (riscv vector spec1.0)
#1808 opened Sep 15, 2024 by latifbhatti
1
Smdbltrp - VS mode double trap check
#1805 opened Sep 13, 2024 by lewislzh
2
Building spike with "--with-priv=m" config option renders spike unusable
#1802 opened Sep 11, 2024 by mkozden
13
SFENCE.VMA instruction privilege
#1798 opened Sep 9, 2024 by Seo-sang
1
RISC-V Standard Spec Trace Support
#1794 opened Aug 30, 2024 by iansseijelly
Logging the value of registers at a certain point during the simulation possible?
#1792 opened Aug 29, 2024 by AshvinVaidyanathan
1
trap instruction page fault error and mode shifting from M-mode to U-mode in spike debug mode
#1790 opened Aug 29, 2024 by kommarisurendra
SPIKE + PK C++ iostream support
#1778 opened Aug 19, 2024 by mp-17
2
Installation Guide for v1.1.0
#1775 opened Aug 16, 2024 by zaki-29871
How to change vector extension configuration(vlen, elen)?
#1767 opened Aug 9, 2024 by Seo-sang
4
Illegal Instruction overlap difference between vfwadd_wf and vwadd_wx
#1766 opened Aug 8, 2024 by FariaaFaheem
1
Need assistance for Executing my targeted workload on spike RISC-V ISA after adding custom trigonometric Instructions
#1747 opened Jul 25, 2024 by baul-iisc
5
SPIKE functions use in System verilog
#1743 opened Jul 23, 2024 by svasekar
2
spike.cfg : remote_bitbang host localhost should be remote_bitbang_host in OPENOCD's
#1739 opened Jul 18, 2024 by yesuweiYYYY
Possible to forward a Ctrl-C to the running program?
#1738 opened Jul 18, 2024 by wsong83
htif : elf load , invalid address
#1737 opened Jul 17, 2024 by svasekar
Dose write-only operation to csr_seed trigger illegal instruction exception ?
#1728 opened Jul 15, 2024 by chihminchao
1
Incorrect IRQ priority with LCOF
#1725 opened Jul 11, 2024 by JJ-Gaisler
Dependency file in makefile is missing
#1723 opened Jul 9, 2024 by hegdeabhi
spike cache model
#1720 opened Jul 2, 2024 by ztjjj9
Use input DTB to set all processor + device configurations properly
#1716 opened Jun 30, 2024 by abejgonzalez
Documentation to add an MMIO device as a plugin
#1708 opened Jun 26, 2024 by Koceilito
1
doubt with vector masking register instruction
#1706 opened Jun 24, 2024 by deepaannnavi
What time the spike will support the zjpm extension?
#1693 opened Jun 14, 2024 by yangye0212
ProTip! Adding no:label will show everything without a label.