Load/Store Pair for RV32 Fast-Track Extension (Zilsd & Zclsd)

This extension adds support for loads and stores using aligned register pairs. It is an RV32-only extension, reusing existing RV64 encodings.

License

This work is licensed under a Creative Commons Attribution 4.0 International License (CC-BY-4.0). See the LICENSE file for details.

Dependencies

To build the document, you’ll need the following tools installed on your system:

• Make

• asciiDoctor-pdf

• Docker

Cloning the Repository

git clone --recurse-submodules https://github.com/riscv/riscv-zilsd.git

VERSION: Represents the version of the specification being built. By default, this is set to 'v0.0.0'. You can change this to a different value, like 'v1.0.0', 'v1.1.0', etc., based on the current version of your specification.

To start the build process, run cd ./riscv-zilsd && make build.

The Makefile script will check the availability of Docker on your system:

• If Docker is available, the documentation will be built inside a Docker container using the image riscvintl/riscv-docs-base-container-image:latest. This ensures a consistent build environment across different systems.

• If Docker is not available, the documentation will be built directly on your system using the installed tools.

The documentation is generated from the AsciiDoctor source files in your project. The primary source file is specified by the HEADER_SOURCE variable in the Makefile.

The build process utilizes several options, including theming and font settings, and generates a PDF document as output.

Cleaning up

To clean up the generated files, run make clean. This will remove the generated PDF file.