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Add support for Hexagon v60 HVX intrinsics #41818

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May 8, 2017
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michaelwu
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HVX is a SIMD coprocessor available on newer hexagon cores. It can be configured for 512 or 1024 bit registers, and some instructions use pairs of registers. It only does integer operations, but it probably has every integer operation you'd want for 8/16/32 bit elements.

There are a lot of intrinsics. The generator outputs 582 of them. I probably got some wrong. I did some scripting to make sure that every llvm intrinsic name exists, but intrinsic names provided for programs have only been compared by eye to Qualcomm's own names. 64/128 is also appended to the names to select between 512/1024 bit. The C intrinsics don't do this, but they only expose one set, selected at compile time.

The json specifying the intrinsics required a bit of duplication since I didn't see an easy way to specify combinations of signed/unsigned types (eg. u(8-16) and s(16-32)). I also didn't see an easy way to specify variants of instructions like saturating or rounding.

Basic multiplication and load/store tested on the hexagon simulator.

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Thanks for the pull request, and welcome! The Rust team is excited to review your changes, and you should hear from @arielb1 (or someone else) soon.

If any changes to this PR are deemed necessary, please add them as extra commits. This ensures that the reviewer can see what has changed since they last reviewed the code. Due to the way GitHub handles out-of-date commits, this should also make it reasonably obvious what issues have or haven't been addressed. Large or tricky changes may require several passes of review and changes.

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nagisa commented May 8, 2017

The changes look fairly straightforward to me. I have a question though. Is Q6 really the prefix used in intrinsics of, say, C compiler(s), to denote the HVX operations?

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Yeah, it's in the documentation and headers. Unfortunately the documentation and headers are buried in their SDK. You can get it from https://developer.qualcomm.com/software/hexagon-dsp-sdk/tools . v3.1 doesn't require registration to download. There's an installer, but you can just unzip it, and then unzip a jar ($SDK$_zg_ia_sf.jar) that's inside. And then the documentation is buried deep in tools/HEXAGON_Tools/8.0.08/Documents/Hexagon_Document_Bundle.pdf. The header is at tools/HEXAGON_Tools/8.0.08/Tools/target/hexagon/include/hvx_hexagon_protos.h. But if you actually want to use the SDK, you have to use the InstallShield installer which also downloads things like the Android SDK.

Pretty terrible.

I think there's one example of an open source project using HVX (halide), but they seem to use llvm ir directly rather than C intrinsics.

It's actually more generic than HVX though - I see the Q6 prefix on other intrinsics too. I'm guessing it's something like Q = Qualcomm, 6 = Hexagon.

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nagisa commented May 8, 2017

@bors r+

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bors commented May 8, 2017

📌 Commit cc4efd1 has been approved by nagisa

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bors commented May 8, 2017

⌛ Testing commit cc4efd1 with merge 70198a0...

bors added a commit that referenced this pull request May 8, 2017
Add support for Hexagon v60 HVX intrinsics

HVX is a SIMD coprocessor available on newer hexagon cores. It can be configured for 512 or 1024 bit registers, and some instructions use pairs of registers. It only does integer operations, but it probably has every integer operation you'd want for 8/16/32 bit elements.

There are a lot of intrinsics. The generator outputs 582 of them. I probably got some wrong. I did some scripting to make sure that every llvm intrinsic name exists, but intrinsic names provided for programs have only been compared by eye to Qualcomm's own names. 64/128 is also appended to the names to select between 512/1024 bit. The C intrinsics don't do this, but they only expose one set, selected at compile time.

The json specifying the intrinsics required a bit of duplication since I didn't see an easy way to specify combinations of signed/unsigned types (eg. u(8-16) and s(16-32)). I also didn't see an easy way to specify variants of instructions like saturating or rounding.

Basic multiplication and load/store tested on the hexagon simulator.
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bors commented May 8, 2017

☀️ Test successful - status-appveyor, status-travis
Approved by: nagisa
Pushing 70198a0 to master...

@bors bors merged commit cc4efd1 into rust-lang:master May 8, 2017
@michaelwu michaelwu deleted the hvx-v60 branch May 17, 2017 19:58
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5 participants