Add support for Ultra96 board

[sgherbst]

This largely depends on #23, since Ultra96 is a board that requires the PL clock to be sourced from the PS. Actually, ULTRA96 is already a board type, but it doesn't work yet, so this task likely involves updating the ULTRA96 class accordingly after #23 is resolved.

anasymod/anasymod/fpga_boards/boards.py

Lines 81 to 91 in fafaa08

	class ULTRA96():
	"""
	Container to store ULTRA96 FPGA board specific properties.
	"""
	clk_pin = ['L19', 'L20']
	clk_io = 'LVDS'
	clk_freq = 26e6
	board_part = None
	full_part_name = 'xczu3eg-sbva484-???'
	short_part_name = 'xczu3eg'
	fpga_sim_ctrl = [FPGASimCtrl.UART_ZYNQ, FPGASimCtrl.VIVADO_VIO]