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23 Open 12 Closed
23 Open 12 Closed
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Issues list

Hello everyone! I’m just starting 😉
#56 opened May 18, 2024 by bassTon05
Delete unused buildkite pipeline/webhook
#55 opened Apr 9, 2024 by steveri
Add support for using SymbiFlow open source tooling instead of Vivado
#54 opened Aug 4, 2021 by mithro
1
Consider using edalize to drive EDA tooling
#53 opened Aug 4, 2021 by mithro
1
Add method to auto-populate sim_ctrl.sv I/Os and initialization
#51 opened Jul 13, 2021 by sgherbst
Add semi-custom firmware option
#50 opened Jul 13, 2021 by sgherbst
Provide method to add user-defined synthesis/implementation constraints
#49 opened Jul 13, 2021 by sgherbst
Provide method to get UART port / PySerial object without programming FPGA
#48 opened Jun 5, 2021 by sgherbst
Provide method to adjust synthesis and implementation effort
#47 opened Jun 5, 2021 by sgherbst
Provide method to treat *.v files as SystemVerilog files in Vivado
#43 opened Jan 28, 2021 by sgherbst
1
Use tree structure to take the minimum of timestep requests
#35 opened Aug 23, 2020 by sgherbst
Make it harder to accidentally delete bitfiles
#34 opened Aug 14, 2020 by sgherbst
Add more descriptive message when xsct cannot be found
#33 opened Aug 12, 2020 by sgherbst
Add support for VCS simulator
#32 opened Aug 7, 2020 by sgherbst
@sgherbst
Update README.md
#30 opened Aug 5, 2020 by sgherbst
Add support for Ultra96 board
#24 opened Jul 10, 2020 by sgherbst
@sgherbst
Add support for running designs from the PS clock.
#23 opened Jul 10, 2020 by sgherbst
@sgherbst
Improve coverage of analysis.py
#20 opened Jun 30, 2020 by sgherbst
Add regression test for EDIF support
#19 opened Jun 30, 2020 by sgherbst
Add more extensive nightly or weekend regression test
#18 opened Jun 30, 2020 by sgherbst
Add tests for new emulation control functions
#17 opened Jun 30, 2020 by sgherbst
Duplicated time points in waveforms from simulation and emulation
#11 opened Apr 25, 2020 by sgherbst
Consider changing the default timescale
#8 opened Apr 25, 2020 by sgherbst
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