This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
A WIP Game Boy Advance emulator.
Virtual memory (VM) manager for 26-bit ARMv3 and ARMv4 based computers running Acorn’s RISC OS
This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.
Genann library port to RISC OS, a simple, fast, reliable and hackable C library for training and using feedforward Artificial Neural Networks (ANN)
Back in 2005 I was a Co-Creator of one of the first Mobile Apps to allow SIM Switching built with C++ using the Windows Mobile SDK and was developed for mobile devices such as for the O2 XDA which were a popular mobile back then.