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Replaced srl overloading with function call to work with Cadence Inci…
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…sive.
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LarsAsplund committed Jan 28, 2016
1 parent 2a32d7c commit 8b09441
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Showing 2 changed files with 4 additions and 4 deletions.
2 changes: 1 addition & 1 deletion setup.py
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ def find_all_files(directory, endings=None):

setup(
name='vunit_hdl',
version='0.51.2',
version='0.51.3',
packages=['vunit',
'vunit.com',
'vunit.test',
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6 changes: 3 additions & 3 deletions vunit/vhdl/check/src/check.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ use work.string_ops.all;

package body check_pkg is
type boolean_vector is array (natural range <>) of boolean;
function "srl" (
function logical_right_shift (
constant arg : boolean_vector;
constant count : natural)
return boolean_vector is
Expand All @@ -28,7 +28,7 @@ package body check_pkg is
ret_val(count to ret_val'right) := temp(0 to ret_val'right - count);

return ret_val;
end function "srl";
end function logical_right_shift;
constant max_supported_num_of_bits_in_integer_implementation : natural := 256;

function failed_expectation_msg (
Expand Down Expand Up @@ -1350,7 +1350,7 @@ package body check_pkg is
else
expected_events(0) := tracks(0);
end if;
expected_events := expected_events srl 1;
expected_events := logical_right_shift(expected_events, 1);
end procedure update_expectations_on_events_in_next_cycle;

procedure verify_expected_events (
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