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Fix regex for VHDL component instantiations #990

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  • Add comments to the multiline regex
  • Extend unittest for vhdl_parser

- Add comments to the multiline regex
- Extend unittest for vhdl_parser
(?:(?:[a-zA-Z]\w*)\.)? # Optional library name
([a-zA-Z]\w*)\s* # Capture component name
(?:generic|port)\s+map\s* # Generic/port map
\(.*?\)\s*; # Open and closing brackets
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Rather than allowing anything between the opening and closing brackets I would suggest extending the previously more restrictive expression with what is needed to pass the new test case:

([\s\w=>,.)(+-'"*/]*)

I cannot recall if the more restrictive expression is there for a reason that is not made explicit in the test cases. For that reason I prefer a more defensive modification.

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Sorry for the delayed reply.
I will modify the regex as you suggested, but I guess there will be other cases in which it won't work

In the mean time I've monkey patched vhdl_parser.py and am matching everything inside the brackets.

@eine eine added this to the v5.0.0 milestone Mar 11, 2024
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