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[release/9.0] Add Non-Faulting behaviour for Sve.LoadVector*NonFaulti…
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…ng*() (#106768)

* Add Non-Faulting behaviour for Sve.LoadVector*NonFaulting*()

Fixes: #105163

* Fix typo

---------

Co-authored-by: Swapnil Gaikwad <swapnil.gaikwad@arm.com>
Co-authored-by: Aman Khalid <amankhalid@microsoft.com>
Co-authored-by: Jeff Schwartz <jeffschw@microsoft.com>
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@github-actions @SwapnilGaikwad
@amanasifkhalid @jeffschwMSFT
4 people committed Aug 22, 2024
1 parent 92707ee commit 7384dc4
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Showing 6 changed files with 266 additions and 82 deletions.
82 changes: 78 additions & 4 deletions src/coreclr/jit/hwintrinsiccodegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -707,10 +707,47 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
{
if (!instrIsRMW)
{
// Perform the actual "predicated" operation so that `embMaskOp1Reg` is the first operand
// and `embMaskOp2Reg` is the second operand.
GetEmitter()->emitIns_R_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg,
embMaskOp2Reg, opt);
// Perform the actual "predicated" operation so that `embMaskOp1Reg` is the first operand..
switch (intrinEmbMask.id)
{
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt16:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt32:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt16:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt32:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt64:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt32:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt64:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt32:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt64:
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToInt64:
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToUInt64:
case NI_Sve_LoadVectorNonFaulting:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt16:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt32:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt64:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt16:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt32:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt64:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt32:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt32:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt64:
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToUInt64:
{

GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg,
opt);
break;
}

default:
{
GetEmitter()->emitIns_R_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg,
embMaskOp2Reg, opt);
}
}
break;
}

Expand Down Expand Up @@ -2142,6 +2179,43 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
break;
}

case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt16:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt32:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt16:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt32:
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt64:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt32:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt64:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt32:
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt64:
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToInt64:
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToUInt64:
case NI_Sve_LoadVectorNonFaulting:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt16:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt32:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt64:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt16:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt32:
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt64:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt32:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt32:
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt64:
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToInt64:
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToUInt64:
{
if (intrin.numOperands == 2)
{
// We have extra argument which means there is a "use" of FFR here. Restore it back in FFR
// register.
assert(op2Reg != REG_NA);
GetEmitter()->emitIns_R(INS_sve_wrffr, emitSize, op2Reg, opt);
}
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op1Reg);
break;
}

case NI_Sve_GatherVectorByteZeroExtendFirstFaulting:
case NI_Sve_GatherVectorFirstFaulting:
case NI_Sve_GatherVectorInt16SignExtendFirstFaulting:
Expand Down
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