Update pulp_platform_common_cells to ef42100

Update code from upstream repository https://github.com/pulp- platform/common_cells.git to revision ef4210009a534cffd0744e981b15e43e7f42c6d6 * CHANGELOG.md: Cleanup (Paul Scheffler) * README.md: Add `addr_decode_napot` (Paul Scheffler) * cleanup: Properly derive `addr_decode_napot` from `addr_decode` (Paul Scheffler) * Add `addr_decode_napot` (Florian Zaruba) * Exclude cb_filter from vivado IP packager projects (#148) (Paul Scheffler) * rstgen_bypass: Use glitch-free `tc_clk_mux` muxes (#147) (Paul Scheffler) * Remove `program` blocks from testbenches for VCS compatibility (#146) (Paul Scheffler) * Add stream_fifo_optimal_wrap (#142) (Thomas Benz) * FuseSoC: Fix IP version (#143) (Hossein Askari) * id_queue: Fix toolproblems (#138) (Samuel Riedel) * Update fusesoc manifest file (#141) (Davide Schiavone) * Update src_files.yml (#137) (glaserf) * Release v1.24.1 (Nils Wistoff) * src_files.yml: Fix typo (#136) (glaserf) * Fix: File name error in Bender.yml (#135) (Michael Rogenmoser) Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>
pulp-platform · Aug 9, 2022 · 302ec12 · 302ec12
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diff --git a/hw/vendor/pulp_platform_common_cells.lock.hjson b/hw/vendor/pulp_platform_common_cells.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/pulp-platform/common_cells.git
-    rev: b5ec8905ed7828655155b0ae971023adf793c600
+    rev: ef4210009a534cffd0744e981b15e43e7f42c6d6
   }
 }
diff --git a/hw/vendor/pulp_platform_common_cells/Bender.yml b/hw/vendor/pulp_platform_common_cells/Bender.yml
@@ -86,6 +86,7 @@ sources:
   - src/id_queue.sv
   - src/stream_to_mem.sv
   - src/stream_arbiter_flushable.sv
+  - src/stream_fifo_optimal_wrap.sv
   - src/stream_register.sv
   - src/stream_xbar.sv
   # Level 3

diff --git a/hw/vendor/pulp_platform_common_cells/CHANGELOG.md b/hw/vendor/pulp_platform_common_cells/CHANGELOG.md
@@ -3,6 +3,19 @@ All notable changes to this project will be documented in this file.
 
 The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
 and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
+## Unreleased
+### Added
+- Add `addr_decode_napot`: variant of `addr_decode` which uses a base address and mask instead of a start and end address.
+
+### Changed
+- Avoid using `$bits()` call in `id_queue`'s parameters.
+- Remove `cb_filter` and `cb_filter_pkg` from from Vivado IP packager project sources due to compatibility issues.
+- Use `tc_clk_mux` as glitch-free muxes in `rstgen_bypass` to avoid combinational glitches.
+- Avoid program blocks in testbenches for simulator compatibility.
+
+## 1.24.1 - 2022-04-13
+### Fixed
+- Fix typos in `Bender.yml` and `src_files.yml`
 
 ## 1.24.0 - 2022-03-31
 ### Added

diff --git a/hw/vendor/pulp_platform_common_cells/README.md b/hw/vendor/pulp_platform_common_cells/README.md
@@ -65,7 +65,8 @@ Please note that cells with status *deprecated* are not to be used for new desig
 
 | Name                       | Description                                                                                               | Status       | Superseded By |
 | -------------------------- | --------------------------------------------------------------------------------------------------------- | ------------ | ------------- |
-| `addr_decode   `           | Address map decoder                                                                                       | active       |               |
+| `addr_decode`              | Address map decoder                                                                                       | active       |               |
+| `addr_decode_napot`        | Address map decoder using naturally-aligned power of two (NAPOT) regions                                  | active       |               |
 | `ecc_decode`               | SECDED Decoder (Single Error Correction, Double Error Detection)                                          | active       |               |
 | `ecc_encode`               | SECDED Encoder (Single Error Correction, Double Error Detection)                                          | active       |               |
 | `binary_to_gray`           | Binary to gray code converter                                                                             | active       |               |
@@ -98,18 +99,19 @@ Please note that cells with status *deprecated* are not to be used for new desig
 
 ### Data Structures
 
-| Name               | Description                                     | Status       | Superseded By |
-| ------------------ | ----------------------------------------------- | ------------ | ------------- |
-| `cb_filter`        | Counting-Bloom-Filter with combinational lookup | active       |               |
-| `fifo`             | FIFO register with upper threshold              | *deprecated* | `fifo_v3`     |
-| `fifo_v2`          | FIFO register with upper and lower threshold    | *deprecated* | `fifo_v3`     |
-| `fifo_v3`          | FIFO register with generic fill counts          | active       |               |
-| `stream_fifo`      | FIFO register with ready/valid interface        | active       |               |
-| `generic_fifo`     | FIFO register without thresholds                | *deprecated* | `fifo_v3`     |
-| `generic_fifo_adv` | FIFO register without thresholds                | *deprecated* | `fifo_v3`     |
-| `sram`             | SRAM behavioral model                           | active       |               |
-| `plru_tree`        | Pseudo least recently used tree                 | active       |               |
-| `unread`           | Empty module to sink unconnected outputs into   | active       |               |
+| Name                       | Description                                                      | Status       | Superseded By |
+| -------------------------- | ---------------------------------------------------------------- | ------------ | ------------- |
+| `cb_filter`                | Counting-Bloom-Filter with combinational lookup                  | active       |               |
+| `fifo`                     | FIFO register with upper threshold                               | *deprecated* | `fifo_v3`     |
+| `fifo_v2`                  | FIFO register with upper and lower threshold                     | *deprecated* | `fifo_v3`     |
+| `fifo_v3`                  | FIFO register with generic fill counts                           | active       |               |
+| `stream_fifo`              | FIFO register with ready/valid interface                         | active       |               |
+| `stream_fifo_optimal_wrap` | Wrapper that optimally selects either a spill register or a FIFO | active       |               |
+| `generic_fifo`             | FIFO register without thresholds                                 | *deprecated* | `fifo_v3`     |
+| `generic_fifo_adv`         | FIFO register without thresholds                                 | *deprecated* | `fifo_v3`     |
+| `sram`                     | SRAM behavioral model                                            | active       |               |
+| `plru_tree`                | Pseudo least recently used tree                                  | active       |               |
+| `unread`                   | Empty module to sink unconnected outputs into                    | active       |               |
 
 
 ## Header Contents

diff --git a/hw/vendor/pulp_platform_common_cells/common_cells.core b/hw/vendor/pulp_platform_common_cells/common_cells.core
@@ -1,6 +1,6 @@
 CAPI=2:
 
-name : pulp-platform.org::common_cells:1.20.0
+name : pulp-platform.org::common_cells:1.24.1
 
 filesets:
   rtl:
@@ -9,18 +9,18 @@ filesets:
       # Source files grouped in levels. Files in level 0 have no dependencies on files in this package.
       # Files in level 1 only depend on files in level 0, files in level 2 on files in levels 1 and 0,
       # etc. Files within a level are ordered alphabetically.
-      # Level 0
       - src/binary_to_gray.sv
       - src/cb_filter_pkg.sv
-      - src/cdc_2phase.sv
+      - src/cc_onehot.sv
       - src/cf_math_pkg.sv
-      - src/clk_div.sv
+      - src/clk_int_div.sv
       - src/delta_counter.sv
       - src/ecc_pkg.sv
       - src/edge_propagator_tx.sv
       - src/exp_backoff.sv
       - src/fifo_v3.sv
       - src/gray_to_binary.sv
+      - src/isochronous_4phase_handshake.sv
       - src/isochronous_spill_register.sv
       - src/lfsr.sv
       - src/lfsr_16bit.sv
@@ -33,7 +33,7 @@ filesets:
       - src/rstgen_bypass.sv
       - src/serial_deglitch.sv
       - src/shift_reg.sv
-      - src/spill_register.sv
+      - src/spill_register_flushable.sv
       - src/stream_demux.sv
       - src/stream_filter.sv
       - src/stream_fork.sv
@@ -44,38 +44,47 @@ filesets:
       - src/sync.sv
       - src/sync_wedge.sv
       - src/unread.sv
+      - src/cdc_reset_ctrlr_pkg.sv
       # Level 1
+      - src/cdc_2phase.sv
+      - src/cdc_4phase.sv
       - src/addr_decode.sv
       - src/cb_filter.sv
       - src/cdc_fifo_2phase.sv
-      - src/cdc_fifo_gray.sv
       - src/counter.sv
       - src/ecc_decode.sv
       - src/ecc_encode.sv
       - src/edge_detect.sv
       - src/lzc.sv
       - src/max_counter.sv
       - src/rstgen.sv
+      - src/spill_register.sv
       - src/stream_delay.sv
       - src/stream_fifo.sv
       - src/stream_fork_dynamic.sv
-      - src/stream_xbar.sv
       # Level 2
+      - src/cdc_reset_ctrlr.sv
+      - src/cdc_fifo_gray.sv
       - src/fall_through_register.sv
       - src/id_queue.sv
       - src/stream_to_mem.sv
       - src/stream_arbiter_flushable.sv
-      - src/stream_omega_net.sv
+      - src/stream_fifo_optimal_wrap.sv
       - src/stream_register.sv
+      - src/stream_xbar.sv
       # Level 3
+      - src/cdc_fifo_gray_clearable.sv
+      - src/cdc_2phase_clearable.sv
       - src/stream_arbiter.sv
+      - src/stream_omega_net.sv
     file_type : systemVerilogSource
 
   deprecated:
     files:
       # Deprecated modules
       # Level 0
       - src/deprecated/clock_divider_counter.sv
+      - src/deprecated/clk_div.sv
       - src/deprecated/find_first_one.sv
       - src/deprecated/generic_LFSR_8bit.sv
       - src/deprecated/generic_fifo.sv
@@ -88,8 +97,9 @@ filesets:
       - src/deprecated/fifo_v2.sv
       # Level 2
       - src/deprecated/fifo_v1.sv
-    
+
       # Depend on deprecated modules
+      - src/edge_propagator_ack.sv
       - src/edge_propagator.sv
       - src/edge_propagator_rx.sv
     file_type : systemVerilogSource

diff --git a/hw/vendor/pulp_platform_common_cells/src/addr_decode.sv b/hw/vendor/pulp_platform_common_cells/src/addr_decode.sv
@@ -23,10 +23,13 @@
 /// for which no rule in `addr_map_i` exists to the default index specified by
 /// `default_idx_i`. In this case, `dec_error_o` is always `1'b0`.
 ///
+/// The `Napot` parameter allows using naturally-aligned power of two (NAPOT) regions,
+/// using base addresses and masks instead of address ranges to specify rules.
+///
 /// Assertions: The module checks every time there is a change in the address mapping
-/// if the resulting map is valid. It fatals if `start_addr` is higher than `end_addr`
-/// or if a mapping targets an index that is outside the number of allowed indices.
-/// It issues warnings if the address regions of any two mappings overlap.
+/// if the resulting map is valid. It fatals if `start_addr` is higher than `end_addr` (non-NAPOT
+/// only) or if a mapping targets an index that is outside the number of allowed indices.
+/// It issues warnings if the address regions of any two mappings overlap (non-NAPOT only).
 module addr_decode #(
   /// Highest index which can happen in a rule.
   parameter int unsigned NoIndices = 32'd0,
@@ -46,7 +49,13 @@ module addr_decode #(
   ///  - `idx`:        index of the rule, has to be < `NoIndices`
   ///  - `start_addr`: start address of the range the rule describes, value is included in range
   ///  - `end_addr`:   end address of the range the rule describes, value is NOT included in range
+  ///
+  /// If `Napot` is 1, The field names remain the same, but the rule describes a naturally-aligned
+  /// power of two (NAPOT) region instead of an address range: `start_addr` becomes the base address
+  /// and `end_addr` the mask. See the wrapping module `addr_decode_napot` for details.
   parameter type         rule_t    = logic,
+  // Whether this is a NAPOT (base and mask) or regular range decoder
+  parameter bit          Napot     = 0,
   /// Dependent parameter, do **not** overwite!
   ///
   /// Width of the `idx_o` output port.
@@ -89,7 +98,11 @@ module addr_decode #(
 
     // match the rules
     for (int unsigned i = 0; i < NoRules; i++) begin
-      if ((addr_i >= addr_map_i[i].start_addr) && (addr_i < addr_map_i[i].end_addr)) begin
+      if (
+        !Napot && (addr_i >= addr_map_i[i].start_addr) && (addr_i < addr_map_i[i].end_addr) ||
+        Napot && (addr_map_i[i].start_addr & addr_map_i[i].end_addr) ==
+                 (addr_i & addr_map_i[i].end_addr)
+      ) begin
         matched_rules[i] = 1'b1;
         dec_valid_o      = 1'b1;
         dec_error_o      = 1'b0;
@@ -126,7 +139,7 @@ module addr_decode #(
   always @(addr_map_i) #0 begin : proc_check_addr_map
     if (!$isunknown(addr_map_i)) begin
       for (int unsigned i = 0; i < NoRules; i++) begin
-        check_start : assume (addr_map_i[i].start_addr < addr_map_i[i].end_addr) else
+        check_start : assume (Napot || addr_map_i[i].start_addr < addr_map_i[i].end_addr) else
           $fatal(1, $sformatf("This rule has a higher start than end address!!!\n\
               Violating rule %d.\n\
               Rule> IDX: %h START: %h END: %h\n\
@@ -143,8 +156,9 @@ module addr_decode #(
             (NoIndices-1)));
         for (int unsigned j = i + 1; j < NoRules; j++) begin
           // overlap check
-          check_overlap : assume (!((addr_map_i[j].start_addr < addr_map_i[i].end_addr) &&
-                                    (addr_map_i[j].end_addr > addr_map_i[i].start_addr)))   else
+          check_overlap : assume (Napot ||
+                                  !((addr_map_i[j].start_addr < addr_map_i[i].end_addr) &&
+                                    (addr_map_i[j].end_addr > addr_map_i[i].start_addr))) else
                $warning($sformatf("Overlapping address region found!!!\n\
               Rule %d: IDX: %h START: %h END: %h\n\
               Rule %d: IDX: %h START: %h END: %h\n\

diff --git a/hw/vendor/pulp_platform_common_cells/src/addr_decode_napot.sv b/hw/vendor/pulp_platform_common_cells/src/addr_decode_napot.sv
@@ -8,25 +8,12 @@
 // CONDITIONS OF ANY KIND, either express or implied. See the License for the
 // specific language governing permissions and limitations under the License.
 
-// Author: Wolfgang Roenninger <wroennin@ethz.ch>
+// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+// Author: Paul Scheffler <paulsc@iis.ee.ethz.ch>
 
-/// Address Decoder: Maps the input address combinatorially to an index.
-/// The address map `addr_map_i` is a packed array of rule_t structs.
-/// The ranges of any two rules may overlap. If so, the rule at the higher (more significant)
-/// position in `addr_map_i` prevails.
-///
-/// There can be an arbitrary number of address rules. There can be multiple
-/// ranges defined for the same index. The start address has to be less than the end address.
-///
-/// There is the possibility to add a default mapping:
-/// `en_default_idx_i`: Driving this port to `1'b1` maps all input addresses
-/// for which no rule in `addr_map_i` exists to the default index specified by
-/// `default_idx_i`. In this case, `dec_error_o` is always `1'b0`.
-///
-/// Assertions: The module checks every time there is a change in the address mapping
-/// if the resulting map is valid. It fatals if `start_addr` is higher than `end_addr`
-/// or if a mapping targets an index that is outside the number of allowed indices.
-/// It issues warnings if the address regions of any two mappings overlap.
+/// This module wraps `addr_decode` in its naturally-aligned power of two (NAPOT) variant,
+/// alleviating the need to set the `Napot` parameter and using more descriptive `rule_t`
+/// field names. See the `addr_decode`documentation for details.
 module addr_decode_napot #(
   /// Highest index which can happen in a rule.
   parameter int unsigned NoIndices = 32'd0,
@@ -35,17 +22,17 @@ module addr_decode_napot #(
   /// Address type inside the rules and to decode.
   parameter type         addr_t    = logic,
   /// Rule packed struct type.
-  /// The address decoder expects three fields in `rule_t`:
+  /// The NAPOT address decoder expects three fields in `rule_t`:
   ///
   /// typedef struct packed {
   ///   int unsigned idx;
   ///   addr_t       base;
   ///   addr_t       mask;
   /// } rule_t;
   ///
-  ///  - `idx`:        index of the rule, has to be < `NoIndices`
-  ///  - `start_addr`: start address of the range the rule describes, value is included in range
-  ///  - `end_addr`:   end address of the range the rule describes, value is NOT included in range
+  ///  - `idx`:   index of the rule, has to be < `NoIndices`.
+  ///  - `base`:  base address whose specified bits should match `addr_i`.
+  ///  - `mask`:  set for bits which are to be checked to determine a match.
   parameter type         rule_t    = logic,
   /// Dependent parameter, do **not** overwite!
   ///
@@ -78,42 +65,29 @@ module addr_decode_napot #(
   input  idx_t                default_idx_i
 );
 
-  logic [NoRules-1:0] matched_rules; // purely for address map debugging
+  // Rename struct field names to those expected by `addr_decode`
+  typedef struct packed {
+    int unsigned  idx;
+    addr_t        start_addr;
+    addr_t        end_addr;
+  } rule_range_t;
 
-  always_comb begin
-    // default assignments
-    matched_rules = '0;
-    dec_valid_o   = 1'b0;
-    dec_error_o   = (en_default_idx_i) ? 1'b0 : 1'b1;
-    idx_o         = (en_default_idx_i) ? default_idx_i : '0;
-
-    // match the rules
-    for (int unsigned i = 0; i < NoRules; i++) begin
-      if ((addr_map_i[i].base & addr_map_i[i].mask) == (addr_i & addr_map_i[i].mask)) begin
-        matched_rules[i] = 1'b1;
-        dec_valid_o      = 1'b1;
-        dec_error_o      = 1'b0;
-        idx_o            = idx_t'(addr_map_i[i].idx);
-      end
-    end
-  end
-
-  // Assumptions and assertions
-  `ifndef VERILATOR
-  // pragma translate_off
-  initial begin : proc_check_parameters
-    assume ($bits(addr_i) == $bits(addr_map_i[0].base)) else
-      $warning($sformatf("Input address has %d bits and address map has %d bits.",
-        $bits(addr_i), $bits(addr_map_i[0].base)));
-    assume (NoRules > 0) else
-      $fatal(1, $sformatf("At least one rule needed"));
-    assume (NoIndices > 0) else
-      $fatal(1, $sformatf("At least one index needed"));
-  end
-
-  assert final ($onehot0(matched_rules)) else
-    $warning("More than one bit set in the one-hot signal, matched_rules");
+  addr_decode #(
+    .NoIndices ( NoIndices    ) ,
+    .NoRules   ( NoRules      ),
+    .addr_t    ( addr_t       ),
+    .rule_t    ( rule_range_t ),
+    .Napot     ( 1            ),
+    .IdxWidth  ( IdxWidth     ),
+    .idx_t     ( idx_t        )
+  ) i_addr_decode (
+    .addr_i,
+    .addr_map_i,
+    .idx_o,
+    .dec_valid_o,
+    .dec_error_o,
+    .en_default_idx_i,
+    .default_idx_i
+);
 
-  // pragma translate_on
-  `endif
 endmodule