x1_and

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Pau Gómez Kabelka edited this page Oct 31, 2019 · 5 revisions

Description

AND gate.

Ports

Name	Direction	Width	Comment
in0	Rx	1 bit
in1	Rx	1 bit
out	Tx	1 bit	out= in0 && in1

Pipeline latency (clk @ 125 MHz)

1 clk cycle.

VHDL