x1_or

Jump to bottom

Pau Gómez Kabelka edited this page Oct 31, 2019 · 4 revisions

Description

Logic OR gate.

Ports

Name	Direction	Width	Comment
in0	Rx	1 bit
in1	Rx	1 bit
out	Tx	1 bit	out=in0 \|\| in1

Pipeline latency (clk @ 125 MHz)

1 clk cycle.

VHDL