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x1_compareNotEqual

Pau Gómez Kabelka edited this page Oct 31, 2019 · 4 revisions

Description

Logic COMPARE NOT EQUAL gate.

Ports

Name Direction Width Comment
in0 Rx 1 bit
in1 Rx 1 bit
out Tx 1 bit out=1 IF in0!=in1
out=0 OTHERWISE

Pipeline latency (clk @ 125 MHz)

1 clk cycle.

VHDL

x1_compareNotEqual.vhd

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